发明申请
- 专利标题： Semiconductor plural gate lengths
- 专利标题（中）： 半导体多个栅极长度
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申请号： US13608211申请日： 2012-09-10
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公开(公告)号： US20140070414A1公开(公告)日： 2014-03-13
- 发明人: Michael J. Hartig , Sivananda K. Kanakasabapathy , Soon-Cheon Seo , Raghavasimhan Sreenivasan
- 申请人： Michael J. Hartig , Sivananda K. Kanakasabapathy , Soon-Cheon Seo , Raghavasimhan Sreenivasan
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L21/283
- IPC分类号： H01L21/283 ; H01L29/49
摘要：
Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.
公开/授权文献
- US08802565B2 Semiconductor plural gate lengths 公开/授权日：2014-08-12
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