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    STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX
    3.
    发明申请
    STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX 审中-公开
    外延生长框架上的应变SOI结构

    公开(公告)号：US20130270638A1

    公开(公告)日：2013-10-17

    申请号：US13445959

    申请日：2012-04-13

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

    摘要： A semiconductor structure includes an epitaxial insulator layer located on a substrate. A fin structure is located on the epitaxial insulator layer, where at least one epitaxial source-drain region having an embedded stressor is located on the epitaxial insulator layer and abuts at least one sidewall associated with the fin structure. The epitaxial source-drain region having the embedded stressor provides stress along the fin structure such that the provided stress is based on a lattice mismatch between the epitaxial source-drain region, and both the epitaxial insulator layer and the one side-wall associated with the fin structure.

    摘要翻译： 半导体结构包括位于衬底上的外延绝缘体层。 翅片结构位于外延绝缘体层上，其中具有嵌入的应力源的至少一个外延源极 - 漏极区域位于外延绝缘体层上并邻接与翅片结构相关联的至少一个侧壁。 具有嵌入的应力源的外延源极 - 漏极区域沿着鳍状结构提供应力，使得所提供的应力基于外延源极 - 漏极区域和外延绝缘体层与与该外部源极 - 漏极区域相关联的一个侧壁之间的晶格失配 翅片结构。

    Electrically controlled optical fuse and method of fabrication
    5.
    发明授权
    Electrically controlled optical fuse and method of fabrication 有权
    电控光熔丝及其制造方法

    公开(公告)号：US08923666B2

    公开(公告)日：2014-12-30

    申请号：US13472674

    申请日：2012-05-16

    申请人： Kangguo Cheng ,  Raghavasimhan Sreenivasan

    发明人： Kangguo Cheng ,  Raghavasimhan Sreenivasan

    IPC分类号： G02B6/42 ,  G02B6/10 ,  G02B26/02

    CPC分类号： G02F1/17 ,  G02B6/10 ,  G02B26/02 ,  H01L31/18

    摘要： Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.

    摘要翻译： 本发明的实施例提供一种电控光熔丝。 光学保险丝以电子方式激活而不是由光源本身激活。 施加的电压导致熔丝温度升高，这导致相变材料从透明变为不透明。 吸收层吸收在转化期间释放的多余原子。

    SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS
    6.
    发明申请
    SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS 有权
    自我调整的联系与改进的鲁棒性

    公开(公告)号：US20140070333A1

    公开(公告)日：2014-03-13

    申请号：US13613436

    申请日：2012-09-13

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/42364 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7833

    摘要： A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor.

    摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上提供功能栅极结构。 栅极侧壁间隔物与功能栅极结构相邻，并且层间介质层邻近栅极侧壁间隔物存在。 栅极导体的上表面相对于层间电介质层凹陷。 多层盖形成了栅极结构的凹陷表面，其中多层盖的至少一层包括高k电介质材料，并且存在于栅侧壁间隔物的侧壁上 功能门结构。 通过开孔蚀刻穿过层间电介质层至少至多层多层盖的高k电介质材料，其中至少高k绝缘材料保护栅极导体的侧壁。

    SELF ALIGNED BORDERLESS CONTACT
    7.
    发明申请
    SELF ALIGNED BORDERLESS CONTACT 有权
    自动对齐无边界联系人

    公开(公告)号：US20140035141A1

    公开(公告)日：2014-02-06

    申请号：US13562341

    申请日：2012-07-31

    申请人： Kangguo Cheng ,  Raghavasimhan Sreenivasan

    发明人： Kangguo Cheng ,  Raghavasimhan Sreenivasan

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76834 ,  H01L21/28518 ,  H01L21/76823 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor structure having a borderless contact, the method including providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate, depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices, depositing a contact level dielectric layer on top of the non-conductive liner, etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner, converting a portion of the non-conductive liner exposed in the contact hole into a conductive liner; and forming a metal contact in the contact hole.

    摘要翻译： 一种制造具有无边界接触的半导体结构的方法，所述方法包括提供与第二半导体器件相邻的第一半导体器件，所述第一和第二半导体器件形成在半导体衬底上，在非导电衬底的顶部上沉积非导电衬垫 半导体衬底和第一和第二半导体器件，在非导电衬垫的顶部上沉积接触电介质层，蚀刻第一半导体器件和第二半导体器件之间的接触电平电介质中的接触孔，并且对 将非接触孔中暴露的非导电衬垫的一部分转换成导电衬垫; 并在接触孔中形成金属接触。

    Self aligned contact with improved robustness
    9.
    发明授权
    Self aligned contact with improved robustness 有权
    自对准接触，改善了坚固性

    公开(公告)号：US09034703B2

    公开(公告)日：2015-05-19

    申请号：US13613436

    申请日：2012-09-13

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

    IPC分类号： H01L21/33 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/42364 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7833

    摘要： A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor.

    摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上提供功能栅极结构。 栅极侧壁间隔物与功能栅极结构相邻，并且层间介质层邻近栅极侧壁间隔物存在。 栅极导体的上表面相对于层间电介质层凹陷。 多层盖形成了栅极结构的凹陷表面，其中多层盖的至少一层包括高k电介质材料，并且存在于栅侧壁间隔物的侧壁上 功能门结构。 通过开孔蚀刻穿过层间电介质层至少至多层多层盖的高k电介质材料，其中至少高k绝缘材料保护栅极导体的侧壁。

    Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs)
    10.
    发明申请
    Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) 有权
    用于调制高K金属栅场效应晶体管（FET）的阈值电压的结构和方法

    公开(公告)号：US20130313643A1

    公开(公告)日：2013-11-28

    申请号：US13478154

    申请日：2012-05-23

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

    IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823835 ,  H01L21/823842

    摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

    摘要翻译： 一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离 存在于第二导电装置区域上的高k栅介质层。 连接栅极导体形成在高k栅介质层的第一部分和第二部分上。 连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。 然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。 用含氧气氛曝光改变暴露的半导体器件的阈值电压。