Invention Application
US20140070843A1 IMPEDANCE CALIBRATION CIRCUIT AND METHOD 审中-公开
阻抗校准电路和方法

IMPEDANCE CALIBRATION CIRCUIT AND METHOD
Abstract:
An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.
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