公开(公告)号：US20140070843A1

公开(公告)日：2014-03-13

申请号：US14075272

申请日：2013-11-08

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Mayank Kumar SINGH ,  Daljeet KUMAR ,  Hiten ADVANI

IPC: H03K19/003

CPC classification number: H03K19/00346 ,  H04L25/0278 ,  H04L25/0298

Abstract: An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

Abstract translation: 实施例包括具有校准器的阻抗校准电路，该校准器被配置为比较外部节点处的电压电平和阻抗校准电路的内部节点，并且基于该比较来生成输出。 校准器还包括耦合在外部节点和比较器的第一输入端之间以及内部节点和比较器的第二输入端之间的相应滤波器。 滤波器被配置为从内部节点处的可编程电阻器耦合到的芯片地线将对称噪声注入到比较器中。

公开(公告)号：US20160187392A1

公开(公告)日：2016-06-30

申请号：US14585357

申请日：2014-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Daljeet KUMAR ,  Tapas NANDY ,  Surendra KUMAR

IPC: G01R19/04

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

Abstract translation: 数据接收设备可以包括包络检测器，其可以包括被配置为接收差分输入信号的第一和第二输入，耦合到第一输入并被配置为产生第一和第二检测器输出的第一对检测器，以及第二对检测器 耦合到第二输入并且被配置为产生第三和第四检测器输出。 包络检测器还可以包括被配置为基于第一和第三检测器产生复位的逻辑电路。 数据接收装置还可以包括耦合到包络检测器的接收器电路，并被配置成随着复位产生基于第二和第四检测器的输出，以及耦合到接收器电路的第一位检测电路。