发明申请
US20140077843A1 Pipelined Bus-Splitting Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesizer System and Method 审中-公开
用于分数N频率合成器的流水线总线分离数字Delta-Sigma调制器系统和方法

Pipelined Bus-Splitting Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesizer System and Method
摘要:
The invention provides a digital modulator system for use in a fractional-N frequency synthesizer, said system comprising: a first pipelined modulator configured to receive a digital signal via a bus signal; a second pipelined modulator configured to receive a part of said digital signal; and said system is adapted to split the bus signal by passing least significant bits (LSBs) of said digital signal through the second modulator, combining the output of said second modulator with the most significant bits (MSBs) of said digital signal, and adapted to pass the combined signal through said first pipelined modulator. The combination of bus-splitting and pipelining in the modulator system is configured to provide an output signal to maximize the update rate of a multi-modulus divider of said fractional-N frequency synthesizer.
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