Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.