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公开(公告)号：US20140089748A1
公开(公告)日：2014-03-27
申请号：US13624706
申请日：2012-09-21
IPC分类号： G01R31/3177
CPC分类号： G01R31/31705
摘要： Systems and techniques for hot-plugging debugger capabilities are described. A described integrated circuit device includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface.
摘要翻译： 描述了用于热插拔调试器功能的系统和技术。 所描述的集成电路设备包括处理器，第一焊盘接口，经配置以经由第一焊盘接口检测时钟信号的检测器，一个或多个第二焊盘接口，两个或多个部件，包括与处理器通信耦合的调试系统 ，多路通信地与所述一个或多个第二焊盘接口和所述两个或更多个部件耦合，并且被配置为选择性地将所述一个或多个第二焊盘接口与所述两个或更多个部件的选定部件相互连接。 当通过第一焊盘接口检测到时钟信号时，多路复用器可被配置为使调试系统成为所选择的部件。
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公开(公告)号：US08726223B2
公开(公告)日：2014-05-13
申请号：US13624706
申请日：2012-09-21
IPC分类号： G06F17/50
CPC分类号： G01R31/31705
摘要： Systems and techniques for hot-plugging debugger capabilities are described. A described integrated circuit device includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface.
摘要翻译： 描述了用于热插拔调试器功能的系统和技术。 所描述的集成电路设备包括处理器，第一焊盘接口，经配置以经由第一焊盘接口检测时钟信号的检测器，一个或多个第二焊盘接口，两个或多个部件，包括与处理器通信耦合的调试系统 ，多路通信地与所述一个或多个第二焊盘接口和所述两个或更多个部件耦合，并且被配置为选择性地将所述一个或多个第二焊盘接口与所述两个或更多个部件的选定部件相互连接。 当通过第一焊盘接口检测到时钟信号时，多路复用器可被配置为使调试系统成为所选择的部件。
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公开(公告)号：US20140089648A1
公开(公告)日：2014-03-27
申请号：US13624651
申请日：2012-09-21
IPC分类号： G06F1/24
CPC分类号： G06F1/24 , G06F11/267
摘要： Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.
摘要翻译： 描述了处理器复位保持控制的系统和技术。 所描述的系统包括控制器，用于基于外部复位信号和外部调试信号检测保持请求，并且基于对保持信号的检测产生保持信号，其中保持信号在外部复位信号已经中断之后继续 ; 响应于外部复位信号的系统组件; 响应于所述保持信号的处理器，其中所述保持信号使所述处理器进入复位状态，并且在所述外部复位信号已经中断之后保持所述复位状态; 以及被配置为在处理器处于复位状态时允许对系统组件的外部访问的系统管理器。 控制器可以被配置为响应于明确的请求中断保持信号。
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4.发明申请Mechanism For Storing And Extracting Trace Information Using Internal Memory In Micro Controllers 有权在微控制器中使用内部存储器存储和提取跟踪信息的机制公开(公告)号：US20120254668A1
公开(公告)日：2012-10-04
申请号：US13527502
申请日：2012-06-19
申请人： Frode Milch Pedersen , Are Arseth
发明人： Frode Milch Pedersen , Are Arseth
IPC分类号： G06F11/34
CPC分类号： G06F11/3636
摘要： This document relates to apparatus and methods to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. Trace data can be retrieved from system memory using a debug port of the debug logic. A system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.
摘要翻译： 本文件涉及在微控制器的片上系统存储器中存储和检索跟踪信息的装置和方法。 微控制器包括微处理器和通过数据总线和耦合到微处理器的地址总线可访问的存储器件。 微控制器包括耦合到微处理器的片上调试逻辑。 可以使用调试逻辑的调试端口从系统内存中检索跟踪数据。 根据本发明的系统将降低在微控制器中实现跟踪特征的成本，并且大大降低了在调试工具中支持这些特征的成本。
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公开(公告)号：US20120161732A1
公开(公告)日：2012-06-28
申请号：US12976049
申请日：2010-12-22
IPC分类号： G05F1/46
CPC分类号： H02M3/156 , H02M2001/0045
摘要： A voltage regulator is configurable to operate in a linear regulator mode or a buck regulator mode. To operate in the buck regulator mode, the voltage regulator is coupled to an inductor. To determine whether an inductor is coupled to voltage regulator, and thus whether the voltage regulator can be configured in the buck regulator mode, a detection circuit determines whether a regulator output of the voltage regulator resists a change in current driven to the regulator output.
摘要翻译： 电压调节器可配置为在线性稳压器模式或降压稳压器模式下工作。 为了在降压调节器模式下工作，电压调节器耦合到电感器。 为了确定电感器是否耦合到电压调节器，并且因此电压调节器是否可以被配置在降压调节器模式中，检测电路确定电压调节器的调节器输出是否抵抗驱动到调节器输出的电流的变化。
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公开(公告)号：US08055963B2
公开(公告)日：2011-11-08
申请号：US13033186
申请日：2011-02-23
CPC分类号： G06F11/2236 , G01R31/318533 , G11C29/48 , G11C29/56 , G11C2029/5602
摘要： System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols.
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7.发明申请MECHANISM FOR STORING AND EXTRACTING TRACE INFORMATION USING INTERNAL MEMORY IN MICRO CONTROLLERS 有权使用微控制器内部存储器存储和提取跟踪信息的机制公开(公告)号：US20100064173A1
公开(公告)日：2010-03-11
申请号：US12616655
申请日：2009-11-11
申请人： Frode Milch Pedersen , Are Arseth
发明人： Frode Milch Pedersen , Are Arseth
CPC分类号： G06F11/3636
摘要： This document relates to apparatus and methods to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. Trace data can be retrieved from system memory using a debug port of the debug logic. A system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.
摘要翻译： 本文件涉及在微控制器的片上系统存储器中存储和检索跟踪信息的装置和方法。 微控制器包括微处理器和通过数据总线和耦合到微处理器的地址总线可访问的存储器件。 微控制器包括耦合到微处理器的片上调试逻辑。 可以使用调试逻辑的调试端口从系统内存中检索跟踪数据。 根据本发明的系统将降低在微控制器中实现跟踪特征的成本，并且大大降低了在调试工具中支持这些特征的成本。
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公开(公告)号：US07506205B2
公开(公告)日：2009-03-17
申请号：US11354340
申请日：2006-02-14
IPC分类号： G06F11/00
CPC分类号： G06F11/2236 , G06F11/3648
摘要： Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from a non-debug mode upon executing a software breakpoint. The system may include a program memory configured to hold instructions for a program, where the software breakpoint replaces at least one of the instructions. The system may also include an instruction replacement register separate from the program memory that is configured to receive the replaced instruction from any of the processor and an external debugger. The system may further include a control component that controls whether the processor fetches a next instruction for execution from the program memory or from the instruction replacement register.
摘要翻译： 提供了用于调试在处理器上执行的程序的方法和系统。 在第一实现中，处理系统包括处理器，其被配置为在执行软件断点时从非调试模式切换到调试模式。 该系统可以包括被配置为保存用于程序的指令的程序存储器，其中软件断点替换指令中的至少一个。 系统还可以包括与程序存储器分离的指令替换寄存器，其被配置为从任何处理器和外部调试器接收替换的指令。 该系统还可以包括控制组件，该控制组件控制处理器是否从程序存储器或从指令替换寄存器获取用于执行的下一个指令。
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公开(公告)号：US07428610B2
公开(公告)日：2008-09-23
申请号：US11353874
申请日：2006-02-14
申请人： Frode Milch Pedersen , Marc Laurent
发明人： Frode Milch Pedersen , Marc Laurent
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203 , G11C16/102 , G11C2216/14 , G11C2216/30
摘要： Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each two-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory.
摘要翻译： 写入闪存的页面可以包括接收基本上独立于闪存的内部架构的写入命令。 在某些实施例中，闪存控制器从遥控器接收两个操作数闪存命令。 在各种实现中，写入过程还可以包括将每个双操作数写入命令转换成依赖于架构的闪存命令; 执行依赖于架构的闪存命令以填充与闪存相关联的页面缓冲器; 随后将页面缓冲器的内容传送到闪存的页面。
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公开(公告)号：US08497741B2
公开(公告)日：2013-07-30
申请号：US13271676
申请日：2011-10-12
IPC分类号： H03L1/00
CPC分类号： H03K3/02315
摘要： A device includes an RC oscillator circuit and incorporates various features that individually and in combination can help improve the stability or accuracy of the oscillator output frequency. The oscillator circuit is operable to provide a tunable output frequency and includes a bias circuit switchable between first and second modes of operation. One of the modes has less drift in oscillator bias current relative to the other mode. The device also includes drift compensation circuitry that is operable to compensate for drift in the oscillator output frequency in a closed-loop mode of operation based on a comparison of the oscillator output frequency with a reference frequency. The device further includes a processor operable to compensate for temperature-based drift in the oscillator frequency in an open-loop mode of operation based on a measured temperature value in the vicinity of the oscillator circuit.
摘要翻译： 一个器件包括一个RC振荡器电路，并结合了各种功能，可以单独和组合使用，有助于提高振荡器输出频率的稳定性或精度。 振荡器电路可操作以提供可调输出频率，并且包括可在第一和第二操作模式之间切换的偏置电路。 其中一种模式相对于其他模式的振荡器偏置电流漂移较小。 该装置还包括漂移补偿电路，其可操作以基于振荡器输出频率与参考频率的比较来补偿在闭环工作模式下的振荡器输出频率中的漂移。 该装置还包括处理器，其可操作以基于振荡器电路附近的测量温度值来补偿基于开环工作模式的振荡器频率中基于温度的漂移。
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