Invention Application
- Patent Title: CLOCK DOMAIN BOUNDARY CROSSING USING AN ASYNCHRONOUS BUFFER
- Patent Title (中): 使用异步缓冲区的时域边界交叉
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Application No.: US13625108Application Date: 2012-09-24
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Publication No.: US20140089718A1Publication Date: 2014-03-27
- Inventor: Julian M. Kain
- Applicant: XILINX, INC.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Main IPC: G06F1/04
- IPC: G06F1/04

Abstract:
An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency to the tap selection circuit of each of the channels. For each of the channels: the latency determination block is coupled to the asynchronous buffer to determine a latency value for the asynchronous buffer; the tap selection circuit is coupled to receive the latency value and the longest latency; the tap selection circuit is coupled to the variable delay; and the tap selection circuit is configured to select a tap of taps of the variable delay responsive to the latency value and the longest latency.
Public/Granted literature
- US09497050B2 Clock domain boundary crossing using an asynchronous buffer Public/Granted day:2016-11-15
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