发明申请
US20140164865A1 ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS
有权
具有减少内存和电源要求的错误修正解码
- 专利标题: ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS
- 专利标题(中): 具有减少内存和电源要求的错误修正解码
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申请号: US14236166申请日: 2011-07-31
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公开(公告)号: US20140164865A1公开(公告)日: 2014-06-12
- 发明人: Eran Sharon , Idan Alrod , Omer Fainzilber , Simon Litsyn
- 申请人: Eran Sharon , Idan Alrod , Omer Fainzilber , Simon Litsyn
- 申请人地址: US TX Plano
- 专利权人: SANDISK TECHNOLOGIES, INC.
- 当前专利权人: SANDISK TECHNOLOGIES, INC.
- 当前专利权人地址: US TX Plano
- 国际申请: PCT/IL2011/000617 WO 20110731
- 主分类号: H03M13/11
- IPC分类号: H03M13/11
摘要:
An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.
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