发明申请
- 专利标题： STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY
- 专利标题（中）： 高k金属门技术的镀层结构与方法
-
申请号： US14167532申请日： 2014-01-29
-
公开(公告)号： US20140170844A1公开(公告)日： 2014-06-19
- 发明人: Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
- 申请人： International Business Machines Corporation
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L21/28
- IPC分类号： H01L21/28
摘要：
A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.
公开/授权文献
信息查询
IPC分类:
