发明申请
- 专利标题： INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR
- 专利标题（中）： 多级无序处理器的指令调度
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申请号： US13993552申请日： 2012-03-30
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公开(公告)号： US20140208074A1公开(公告)日： 2014-07-24
- 发明人: Boris A. Babayan , Vladimir Pentkovski , Jayesh Iyer , Nikolay Kosarev , Sergey Y. Shishlov , Alexander V. Butuzov , Alexey Y. Sivtsov
- 申请人： Boris A. Babayan , Vladimir Pentkovski , Jayesh Iyer , Nikolay Kosarev , Sergey Y. Shishlov , Alexander V. Butuzov , Alexey Y. Sivtsov
- 国际申请： PCT/US12/31474 WO 20120330
- 主分类号： G06F9/30
- IPC分类号： G06F9/30
摘要：
In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed.
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