发明申请
- 专利标题： CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN NANOWIRE TRANSISTORS
- 专利标题（中）： 联系技术和配置降低纳米晶体管的抗电弧性
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申请号： US13997897申请日： 2011-12-28
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公开(公告)号： US20140209865A1公开(公告)日： 2014-07-31
- 发明人: Ravi Pillarisetty , Benjamin Chu-Kung , Willy Rachmady , Van H. Le , Gilbert Dewey , Niloy Mukherjee , Matthew V. Metz , Han Wui Then , Marko Radosavljevic
- 申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Willy Rachmady , Van H. Le , Gilbert Dewey , Niloy Mukherjee , Matthew V. Metz , Han Wui Then , Marko Radosavljevic
- 国际申请： PCT/US2011/067667 WO 20111228
- 主分类号： H01L29/775
- IPC分类号： H01L29/775 ; H01L29/66
摘要：
Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.
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