Invention Application
- Patent Title: METHODS FOR FABRICATING INTEGRATED CIRCUITS THAT INCLUDE A SEALED SIDEWALL IN A POROUS LOW-K DIELECTRIC LAYER
- Patent Title (中): 在多孔低介电层包括密封小屋的集成电路的制作方法
-
Application No.: US13841855Application Date: 2013-03-15
-
Publication No.: US20140273463A1Publication Date: 2014-09-18
- Inventor: Denis Shamiryan , Adam Michal Urbanowicz
- Applicant: GLOBALFOUNDRIES, INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee: GLOBALFOUNDRIES, Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L21/311
- IPC: H01L21/311

Abstract:
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a sidewall in a porous low-k dielectric layer that overlies a semiconductor substrate using a plurality of discontinuous etching treatments. Exposed portions of the sidewall are progressively sealed interposingly between the discontinuous etching treatments to form a sealed sidewall. The sealed sidewall defines a trench in the porous low-k dielectric layer.
Information query
IPC分类: