A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.