Invention Application
US20140281641A1 METHOD AND APPARATUS FOR CONTROLLED RESET SEQUENCES WITHOUT PARALLEL FUSES AND PLL'S
有权
用于不具有并联熔丝和PLL的控制复位序列的方法和装置
- Patent Title: METHOD AND APPARATUS FOR CONTROLLED RESET SEQUENCES WITHOUT PARALLEL FUSES AND PLL'S
- Patent Title (中): 用于不具有并联熔丝和PLL的控制复位序列的方法和装置
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Application No.: US13844824Application Date: 2013-03-16
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Publication No.: US20140281641A1Publication Date: 2014-09-18
- Inventor: Ivan Herrera Mejia , Vishram Sarurkar , Vijay K. Vuppaladadium
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F1/24
- IPC: G06F1/24
Abstract:
A system, semiconductor device and method for providing a controlled system reset sequence with lower power consumption without dependency on fuses, PLL's and external XTAL's. A method to simplify a boot sequence by using a ring oscillator that compensates for voltage and temperature variations while also removing the dependency on parallel fuses, PLL's and external XTAL's.
Public/Granted literature
- US09223365B2 Method and apparatus for controlled reset sequences without parallel fuses and PLL'S Public/Granted day:2015-12-29
Information query
