发明申请
US20140284695A1 VERTICAL CELL-TYPE SEMICONDUCTOR DEVICE HAVING PROTECTIVE PATTERN
有权
具有保护图案的垂直细胞型半导体器件
- 专利标题: VERTICAL CELL-TYPE SEMICONDUCTOR DEVICE HAVING PROTECTIVE PATTERN
- 专利标题(中): 具有保护图案的垂直细胞型半导体器件
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申请号: US14151288申请日: 2014-01-09
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公开(公告)号: US20140284695A1公开(公告)日: 2014-09-25
- 发明人: Jin-Yeon WON , Joon-Hee LEE , Seung-Woo PAEK , Dong-Seog EUN
- 申请人: Jin-Yeon WON , Joon-Hee LEE , Seung-Woo PAEK , Dong-Seog EUN
- 优先权: KR10-2013-0029103 20130319
- 主分类号: H01L29/792
- IPC分类号: H01L29/792
摘要:
According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.
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