发明申请
- 专利标题: CHIP DIODE AND DIODE PACKAGE
- 专利标题(中): 芯片二极管和二极管封装
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申请号: US14349901申请日: 2012-10-16
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公开(公告)号: US20140284754A1公开(公告)日: 2014-09-25
- 发明人: Hiroki Yamamoto
- 申请人: ROHM CO., LTD.
- 申请人地址: JP Kyoto JP Kyoto
- 专利权人: ROHM CO., LTD.,ROHM CO., LTD.
- 当前专利权人: ROHM CO., LTD.,ROHM CO., LTD.
- 当前专利权人地址: JP Kyoto JP Kyoto
- 优先权: JP2011-227964 20111017; JP2011-270253 20111209; JP2012-060557 20120316; JP2012-060558 20120316; JP2012060559 20120316; JP2012-086784 20120405; JP2012-148862 20120702; JP2012-149732 20120703; JP2012-149733 20120703; JP2012-149734 20120703; JP2012-217882 20120928
- 国际申请: PCT/JP2012/076684 WO 20121016
- 主分类号: H01L29/417
- IPC分类号: H01L29/417 ; H01L29/861
摘要:
[Theme] To provide a chip diode, with which a p-n junction formed on a semiconductor layer can be prevented from being destroyed and fluctuations in characteristics can be suppressed even when a large stress is applied to a pad for electrical connection with the exterior, and a diode package that includes the chip diode.[Solution] A chip diode 15 includes an epitaxial layer 21 with a p-n junction 28, constituting a diode element 29, formed therein, an anode electrode 34 disposed along a top surface 22 of the epitaxial layer 21, electrically connected to a diode impurity region 23, which is the p-side pole of the p-n junction 28, and having a pad 37 for electrical connection with the exterior, and a cathode electrode 41 electrically connected to the epitaxial layer 21, which is the n-side pole of the p-n junction 28, and the pad 37 is provided at a position separated from a position directly above the p-n junction 28.
公开/授权文献
- US09054072B2 Chip diode and diode package 公开/授权日:2015-06-09
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