Invention Application
- Patent Title: MINIMIZING PRINTED CIRCUIT BOARD WARPAGE
- Patent Title (中): 打印印刷电路板最小化
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Application No.: US13849580Application Date: 2013-03-25
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Publication No.: US20140285979A1Publication Date: 2014-09-25
- Inventor: Bruce J. Chamberlin , Joseph P. Kuczynski , Paula M. Nixa
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H05K1/02
- IPC: H05K1/02

Abstract:
A printed circuit board and method of manufacturing same, the printed circuit board comprising a stack of layers. The stack of layers being comprised of alternating circuit layers and insulating layers that are laminated together. The stack of layers includes an area with resin cured to a degree. The area has a coefficient of thermal expansion that is dependent, at least in part, on the degree of curing of the resin.
Public/Granted literature
- US10194537B2 Minimizing printed circuit board warpage Public/Granted day:2019-01-29
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