Invention Application
US20140295655A1 METHOD FOR FORMING THROUGH-SILICON VIA (TSV) WITH DIFFUSED ISOLATION WELL
审中-公开
通过具有扩散隔离层(TSV)形成通过硅的方法
- Patent Title: METHOD FOR FORMING THROUGH-SILICON VIA (TSV) WITH DIFFUSED ISOLATION WELL
- Patent Title (中): 通过具有扩散隔离层(TSV)形成通过硅的方法
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Application No.: US14301133Application Date: 2014-06-10
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Publication No.: US20140295655A1Publication Date: 2014-10-02
- Inventor: Chi-Yeh YU
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: H01L21/768
- IPC: H01L21/768

Abstract:
A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance.
Public/Granted literature
- US09214390B2 Method for forming through-silicon via (TSV) with diffused isolation well Public/Granted day:2015-12-15
Information query
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