公开(公告)号：US20140096102A1

公开(公告)日：2014-04-03

申请号：US13683901

申请日：2012-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-min FU ,  William Wu SHEN ,  Po-Hsiang HUANG ,  Meng-Fu YOU ,  Chi-Yeh YU

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F2217/40 ,  G06F2217/80

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, inputting a power profile in a computer processor, generating a transient temperature profile based on the 3D-IC model, identifying a potential thermal violation at a corresponding operating time interval and a corresponding location of a plurality of points of the 3D-IC design, and outputting data representing the potential thermal violation. The 3D-IC model represents a 3D-IC design comprising a plurality of elements in a stack configuration. The power profile is applied to the plurality of elements of the 3D-IC design as a function of an operating time. The transient temperature profile includes temperatures at a plurality of points of the 3D-IC design as a function of an operating time.

Abstract translation: 计算机实现的方法包括访问存储在有形的，非暂时的机器可读介质中的3D-IC模型，在计算机处理器中输入功率分布，基于3D-IC模型生成瞬态温度分布，识别潜在的热违规 在相应的操作时间间隔和3D-IC设计的多个点的对应位置，并输出表示潜在的热违规的数据。 3D-IC模型表示包括堆叠配置中的多个元件的3D-IC设计。 功率分布作为操作时间的函数应用于3D-IC设计的多个元件。 瞬态温度分布包括作为操作时间的函数的3D-IC设计的多个点处的温度。

公开(公告)号：US20140101626A1

公开(公告)日：2014-04-10

申请号：US14101448

申请日：2013-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yeh YU ,  Chung-Min FU ,  Ping-Heng YEH

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5081

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

Abstract translation: 计算机实现的方法包括访问存储在有形的，非暂时的机器可读介质中的3D-IC模型，在计算机处理器中处理该模型以产生包含在操作下的3D-IC的多个点处的温度的温度图 条件; 识别电迁移（EM）额定因子，以及从处理器计算和输出表示每个点处的温度依赖EM电流约束的数据。

公开(公告)号：US20160004809A1

公开(公告)日：2016-01-07

申请号：US14857212

申请日：2015-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Shen LIN ,  Jerry Chang-Jui KAO ,  Nitesh KATTA ,  Chou-Kun LIN ,  Yi-Chuin TSAI ,  Chi-Yeh YU ,  Kuo-Nan YANG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  G06F2217/82 ,  H01L23/5226 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

公开(公告)号：US20150095864A1

公开(公告)日：2015-04-02

申请号：US14098435

申请日：2013-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Shen LIN ,  Jerry Chang-Jui KAO ,  Nitesh KATTA ,  Chou-Kun LIN ,  Yi-Chuin TSAI ,  Chi-Yeh YU ,  Kuo-Nan YANG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  G06F2217/82 ,  H01L23/5226 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

Abstract translation: 公开了一种包括以下概述的操作的方法。 当金属片段的第一端和第二端周围的第一电流和第二电流的方向分别相反时，第一标准被确定为满足，其中金属片段是至少一个中的电源轨的一部分 半导体器件的设计文件，仅由两个端子通孔阵列封装。 当金属段的长度不大于电迁移临界长度时，确定满足第二标准。 当符合第一和第二标准时，金属段被包括在半导体器件中，具有取决于金属段的长度的第一电流密度极限。

公开(公告)号：US20210042461A1

公开(公告)日：2021-02-11

申请号：US16885657

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yi HU ,  Chih-Ming CHAO ,  Chi-Yeh YU

IPC: G06F30/392 ,  H01L27/02 ,  H01L29/423 ,  G06F30/398

Abstract: Methods for inserting dummy boundary cells in an integrated circuit (IC) are provided. A plurality of macros and a top channel are merged into floorplan of the IC. The top channel is arranged between the macros and is filled with a plurality of first dummy boundary cells, and each of the macros includes a macro boundary and a main pattern surrounded by the macro boundary. The first dummy boundary cells within the top channel and between a first macro and a second macro are replaced with a plurality of second dummy boundary cells. The macro boundaries of the first and second macros are formed by the second dummy boundary cells. First gate length of dummy patterns within the first dummy boundary cells is greater than second gate length of dummy patterns within the second dummy boundary cells. The first and second dummy boundary cells are the same size.

公开(公告)号：US20140295655A1

公开(公告)日：2014-10-02

申请号：US14301133

申请日：2014-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yeh YU

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76828 ,  H01L21/76898 ,  H01L23/481 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance.

Abstract translation: 半导体器件及其形成方法提供了由电介质衬垫包围的硅通孔（TSV）。 TSV和电介质衬垫被由热扩散形成的阱区围绕。 阱区域包括与衬底的掺杂剂杂质类型相反的掺杂剂杂质类型。 阱区可以是具有由第一材料形成并具有第一浓度的内部部分和由具有第二浓度的第二材料形成的外部部分的双扩散井。 周围的阱区用作隔离阱，减少寄生电容。