A semiconductor device disclosed in this specification includes a p+ contact region, an n+ source region, a p− base region, an n− drift region, a gate electrode, an insulator, a p+ electric field alleviating layer, and a p− positive hole extraction region. The electric field alleviating layer has same impurity concentration as the base region or higher, contacts a lower surface of the base region, and is formed in a same depth as the gate trench or in a position deeper than the gate trench. A positive hole extraction region extends to contact the electric field alleviating layer from a position to contact an upper surface of a semiconductor substrate or a first semiconductor region, and extracts a positive hole that is produced in the electric field alleviating layer at the avalanche breakdown to the upper surface of the semiconductor substrate.