发明申请
US20140332956A1 INTEGRATED CIRCUIT PACKAGE WITH SPATIALLY VARIED SOLDER RESIST OPENING DIMENSION
有权
具有空间变化的焊接电阻开放尺寸的集成电路封装
- 专利标题: INTEGRATED CIRCUIT PACKAGE WITH SPATIALLY VARIED SOLDER RESIST OPENING DIMENSION
- 专利标题(中): 具有空间变化的焊接电阻开放尺寸的集成电路封装
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申请号: US13893193申请日: 2013-05-13
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公开(公告)号: US20140332956A1公开(公告)日: 2014-11-13
- 发明人: Tieyu ZHENG , Sumit KUMAR , Sridhar NARA , Renee D. GARCIA , Manohar S. KONCHADY , Suresh B. YERUVA , Lynn H. CHEN , Tyler N. OSBORN , Sairam AGRAHARAM
- 申请人: Tieyu ZHENG , Sumit KUMAR , Sridhar NARA , Renee D. GARCIA , Manohar S. KONCHADY , Suresh B. YERUVA , Lynn H. CHEN , Tyler N. OSBORN , Sairam AGRAHARAM
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L21/768
摘要:
An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).
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