公开(公告)号：US20140332956A1

公开(公告)日：2014-11-13

申请号：US13893193

申请日：2013-05-13

申请人： Tieyu ZHENG ,  Sumit KUMAR ,  Sridhar NARA ,  Renee D. GARCIA ,  Manohar S. KONCHADY ,  Suresh B. YERUVA ,  Lynn H. CHEN ,  Tyler N. OSBORN ,  Sairam AGRAHARAM

发明人： Tieyu ZHENG ,  Sumit KUMAR ,  Sridhar NARA ,  Renee D. GARCIA ,  Manohar S. KONCHADY ,  Suresh B. YERUVA ,  Lynn H. CHEN ,  Tyler N. OSBORN ,  Sairam AGRAHARAM

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/81 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0603 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1413 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

摘要： An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).

摘要翻译： 具有通过焊料互连的第一和第二衬底的集成电路（IC）封装堆栈还包括混合侧向尺寸的阻焊剂开口（SRO）在衬底的一个区域上空间变化。 在实施例中，SRO尺寸在至少两个不同直径之间变化，作为取决于衬底区域内的位置的衬底之间的估计间隙的函数。 在至少一个衬底中的偏转减小衬底之间的共形性的实施例中，通过在较小间隙的区域中相对于SRO尺寸的较大间隙的区域中减小SRO的横向尺寸，从固定体积的焊料提供变化的焊点高度 。 在实施例中，第一基板可以是IC芯片，封装基板或插入件中的任何一个，而第二基板可以是另一个IC芯片，封装基板，插入件或印刷电路板（PCB）中的任何一个。

公开(公告)号：US20150001740A1

公开(公告)日：2015-01-01

申请号：US13930889

申请日：2013-06-28

申请人： Hualiang SHI ,  Shengquan E. OU ,  Sairam AGRAHARAM ,  Tyler N. OSBORN

发明人： Hualiang SHI ,  Shengquan E. OU ,  Sairam AGRAHARAM ,  Tyler N. OSBORN

IPC分类号： H01L21/768 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/3114 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/113 ,  H01L2224/11428 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads; and depositing solder on the accessible area of the contact pads. An apparatus including an integrated circuit substrate including a body having a nonplanar shape and a surface including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads.

摘要翻译： 一种包括在集成电路基板上形成接触焊盘阵列的方法，所述接触焊盘阵列包括第一多个接触焊盘和第二多个接触焊盘，其中所述第一多个接触焊盘中的每一个的可访问区域不同于 第二多个接触垫中的每一个的可访问区域; 以及将焊料沉积在接触垫的可接近区域上。 一种装置，包括集成电路基板，其包括具有非平面形状的主体和包括第一多个接触焊盘和第二多个接触焊盘的表面，其中，所述第一多个接触焊盘中的每一个的可访问区域不同于可访问的 每个第二多个接触垫的面积。