发明申请
- 专利标题： GATE ROUNDING FOR REDUCED TRANSISTOR LEAKAGE CURRENT
- 专利标题（中）： 用于降低晶体管漏电流的栅极绕组
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申请号： US14365007申请日： 2011-12-14
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公开(公告)号： US20140346606A1公开(公告)日： 2014-11-27
- 发明人: Yanfei Cai , Ji Li
- 申请人： Yanfei Cai , Ji Li
- 申请人地址： US CA San Diego
- 专利权人： QUALCOMM Incorporated
- 当前专利权人： QUALCOMM Incorporated
- 当前专利权人地址： US CA San Diego
- 国际申请： PCT/CN2011/083934 WO 20111214
- 主分类号： H01L29/423
- IPC分类号： H01L29/423 ; H01L21/28 ; H01L27/088 ; H01L29/49 ; H01L29/78
摘要：
Gate-rounding fabrication techniques can be implemented to increase an effective channel length of a transistor and to consequently reduce the leakage current and static power consumption associated with the transistor. The transistor comprises a substrate region that includes a source region and a drain region. The transistor can also comprise a gate region that includes a main gate portion, one or more gate tips, and one or more corresponding gate-rounded portions. Each of the one or more gate tips is formed at a suitable position along the side of the main gate portion. During fabrication, the junction between the main gate region and each of the gate tips takes on a rounded shape to form a corresponding gate-rounded region. The gate-rounded regions increase the average length of the gate region and the effective channel length of the transistor.
公开/授权文献
- US09153659B2 Gate rounding for reduced transistor leakage current 公开/授权日：2015-10-06
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