Invention Application
- Patent Title: FIN PITCH SCALING AND ACTIVE LAYER ISOLATION
- Patent Title (中): FIN PITCH SCALING和主动层隔离
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Application No.: US14011125Application Date: 2013-08-27
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Publication No.: US20150061014A1Publication Date: 2015-03-05
- Inventor: Ajey Poovannummoottil JACOB , Murat Kerem AKARVARDAR , Steven John BENTLEY , Bartlomiej Jan PAWLAK
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L21/764
- IPC: H01L21/764 ; H01L21/02 ; H01L29/78

Abstract:
A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.
Public/Granted literature
- US09076842B2 Fin pitch scaling and active layer isolation Public/Granted day:2015-07-07
Information query
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