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    DUAL-WIDTH FIN STRUCTURE FOR FINFETS DEVICES
    1.
    发明申请
    DUAL-WIDTH FIN STRUCTURE FOR FINFETS DEVICES 审中-公开
    FINFET设备的双宽度结构

    公开(公告)号：US20160027775A1

    公开(公告)日：2016-01-28

    申请号：US14341423

    申请日：2014-07-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem AKARVARDAR ,  Ajey P. JACOB ,  Andreas KNORR

    IPC: H01L27/088 ,  H01L29/161 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/49

    CPC classification number: H01L29/66545 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/161 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method of forming a FinFET device having Si or high Ge concentration SiGe fins with a narrow width under the gate and a wider width under the spacer and the resulting device are provided. Embodiments include forming fins; forming a dummy gate, with a dummy oxide thereunder and a nitride HM on top, on the fins, the dummy gate formed perpendicular to the fins; forming a nitride spacer on each side of the dummy gate; forming an oxide in-between adjacent gates and planarizing; removing the nitride HM and dummy gate, forming a channel between the nitride spacers; oxidizing the fins in the channel; removing the dummy oxide and oxidized portions of the fins; and forming a RMG on the fins between the nitride spacers.

    Abstract translation: 提供了一种形成具有Si或高Ge浓度SiGe鳍的FinFET器件的方法，该栅极在栅极下方具有窄的宽度，并且在间隔物和形成的器件下形成更宽的宽度。 实施例包括形成翅片; 在翅片上形成虚拟栅极，其上具有虚拟氧化物和顶部​​的氮化物HM，垂直于鳍片形成的虚拟栅极; 在所述虚拟栅极的每一侧上形成氮化物间隔物; 在相邻栅极之间形成氧化物并平坦化; 去除氮化物HM和虚拟栅极，在氮化物间隔物之间​​形成通道; 氧化通道中的翅片; 去除虚拟氧化物和翅片的氧化部分; 并在氮化物间隔物之间​​的翅片上形成RMG。

    FINFET WITH INSULATOR UNDER CHANNEL
    2.
    发明申请
    FINFET WITH INSULATOR UNDER CHANNEL 有权
    带绝缘体的FINFET通道

    公开(公告)号：US20150021663A1

    公开(公告)日：2015-01-22

    申请号：US13945627

    申请日：2013-07-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Murat Kerem AKARVARDAR ,  Jody A. Fronheiser ,  Ajey Poovannummoottil JACOB

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

    Abstract translation: FinFET具有包括半导体衬底，半导体鳍片和横跨翅片的栅极的结构。 翅片各自具有连接到基底的底部区域和顶部活动区域。 位于底部和顶部翅片区域之间的是中间堆叠，位于垂直细长的源和垂直细长的排水管之间。 堆叠包括顶部通道区域和紧邻通道区域下方的电介质区域，提供通道的电隔离。 部分隔离结构可以与栅极第一和栅极末端制造工艺一起使用。

    REDUCING RISK OF PUNCH-THROUGH IN FINFET SEMICONDUCTOR STRUCTURE
    3.
    发明申请
    REDUCING RISK OF PUNCH-THROUGH IN FINFET SEMICONDUCTOR STRUCTURE 有权
    降低FINFET半导体结构中的PUNCH-THROUGH的风险

    公开(公告)号：US20160268260A1

    公开(公告)日：2016-09-15

    申请号：US15051420

    申请日：2016-02-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kwanyong LIM ,  Murat Kerem AKARVARDAR

    IPC: H01L27/092 ,  H01L29/167 ,  H01L21/8238

    CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L29/167

    Abstract: Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.

    Abstract translation: 减少在FinFET结构中穿透的机会包括提供衬底，在衬底上产生其中杂质的半导体材料的覆盖层，掩蔽覆盖层的一部分，在结构的未屏蔽部分上产生外延半导体材料， 去除掩模，并蚀刻该结构以产生n型凸起结构和p型凸起结构，凸起结构的底部被隔离材料包围。 凸起结构的中间部分包括其中具有杂质的半导体材料，中间部分延伸穿过凸起结构，以及包括不含添加杂质的半导体材料的顶部。

    METHODS OF FORMING TRANSISTOR STRUCTURES
    4.
    发明申请
    METHODS OF FORMING TRANSISTOR STRUCTURES 有权
    形成晶体结构的方法

    公开(公告)号：US20160190289A1

    公开(公告)日：2016-06-30

    申请号：US14883045

    申请日：2015-10-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem AKARVARDAR ,  Steven BENTLEY

    IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06

    CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/32134 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/785

    Abstract: Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure.

    Abstract translation: 提供了制造晶体管结构的方法，所述方法包括：形成具有上翅片部分和下翅片部分的翅片结构，所述上翅片部分包括牺牲材料; 在翅片上形成栅极结构; 选择性地去除所述上翅片部分以在所述门结构和所述下翅片部分之间形成隧道; 以及在隧道中提供通道材料以限定栅极结构的沟道区域。 牺牲材料可以是可以选择性地蚀刻而不蚀刻下部翅片部分的材料的材料。 可以进一步提供沟道材料以形成晶体管结构的源极和漏极区域，这可能导致无连接的FinFET结构。

    FINFET WITH ELECTRICALLY ISOLATED ACTIVE REGION ON BULK SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING SAME
    5.
    发明申请
    FINFET WITH ELECTRICALLY ISOLATED ACTIVE REGION ON BULK SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING SAME 有权
    在半导体基片上具有电分离的有源区的FINFET及其制造方法

    公开(公告)号：US20150021691A1

    公开(公告)日：2015-01-22

    申请号：US13945455

    申请日：2013-07-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER ,  Ajey Poovannummoottil JACOB

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795

    Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET. The oxidized sacrificial layer under the active channel prevents punch-through leakage in the final FinFET structure.

    Abstract translation: FinFET的半导体堆叠制造包括体硅衬底，在主体衬底上的可选择性氧化的牺牲层和牺牲层上的活性硅层。 翅片从有源层，牺牲层和体硅的堆叠中蚀刻出来。 制造保形氧化物沉积来封装散热片，例如使用HARP沉积。 依靠具有比有源层或衬底高得多的氧化速率的牺牲层，例如通过退火进行牺牲层的选择性氧化。 保形氧化物的存在为翅片提供结构稳定性，并防止在氧化过程中翅片的倾斜。 牺牲层的选择性氧化提供顶部有源硅层与散热片的体硅部分的电隔离，导致类SOI结构。 然后进一步制造可以将有源层转换成FinFET的源极，漏极和沟道。 有源通道下方的氧化牺牲层可防止最终的FinFET结构中的穿透泄漏。

    ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MATERIALS AND FABRICATION METHODS
    8.
    发明申请
    ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MATERIALS AND FABRICATION METHODS 审中-公开

    公开(公告)号：US20180138079A1

    公开(公告)日：2018-05-17

    申请号：US15848371

    申请日：2017-12-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER

    IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04

    CPC classification number: H01L21/76202 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

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