Invention Application
US20150083986A1 METHODS OF FORMING SEMICONDUCTOR DEVICES AND STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RESULTING STRUCTURES AND SEMICONDUCTOR DEVICES 有权
形成具有改进的平面化均匀性的半导体器件和结构的方法,以及结构和半导体器件

  • Patent Title: METHODS OF FORMING SEMICONDUCTOR DEVICES AND STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RESULTING STRUCTURES AND SEMICONDUCTOR DEVICES
  • Patent Title (中): 形成具有改进的平面化均匀性的半导体器件和结构的方法,以及结构和半导体器件
  • Application No.: US14038164
    Application Date: 2013-09-26
  • Publication No.: US20150083986A1
    Publication Date: 2015-03-26
  • Inventor: Giulio Albini
  • Applicant: Micron Technology, Inc.
  • Applicant Address: US ID Boise
  • Assignee: Micron Technology, Inc.
  • Current Assignee: Micron Technology, Inc.
  • Current Assignee Address: US ID Boise
  • Main IPC: H01L45/00
  • IPC: H01L45/00
METHODS OF FORMING SEMICONDUCTOR DEVICES AND STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RESULTING STRUCTURES AND SEMICONDUCTOR DEVICES
Abstract:
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.
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