Invention Application
US20150095580A1 SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS
审中-公开
规范机制，以实施向地址写入的监视器的指令
- Patent Title: SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS
- Patent Title (中): 规范机制，以实施向地址写入的监视器的指令
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Application No.: US14040375Application Date: 2013-09-27
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Publication No.: US20150095580A1Publication Date: 2015-04-02
- Inventor: Yen-Cheng Liu , Bahaa Fahim , Erik G. Hallnor , Jeffrey D. Chamberlain , Stephen R. Van Doren , Antonio Juan
- Applicant: Intel Corporation
- Main IPC: G06F12/08
- IPC: G06F12/08
Abstract:
A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.
Public/Granted literature
- US10705961B2 Scalably mechanism to implement an instruction that monitors for writes to an address Public/Granted day:2020-07-07
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