A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform having an appearance corresponding to a location of the cursor. The signal wave overlay indicates a desired value of the signal at one or more clock cycles that is different than the actual value of the signal in the one or more clock cycles. Based on the desired value of the signal indicated by the signal wave overlay, a visualization constraint for the circuit design is generated. The visualization constraint is used to generate a second waveform, where the visualization constraint restricts the second waveform.