公开(公告)号：US09449196B1

公开(公告)日：2016-09-20

申请号：US13867341

申请日：2013-04-22

Applicant: Jasper Design Automation, Inc.

Inventor： Victor Markus Purri ,  Caio Araújo Teixeira Campos ,  Magnus Björk ,  Lawrence Loh ,  Claudionor Jose Nunes Coelho

IPC: G06F9/455 ,  G06F17/50 ,  G06F21/70

CPC classification number: G06F21/71 ,  G06F17/5022 ,  G06F17/5045 ,  G06F21/76

Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

Abstract translation: 形式验证方法通过证明电路设计的路径覆盖属性的不可达性来验证电路设计中的数据访问和数据传播路径。 安全路径验证系统接收电路设计的原始电路模型，以及标识电路设计中作为污染数据源的第一位置和耦合到第一位置的电路​​设计内的第二位置的参数。 安全路径验证系统还接收要从验证分析中排除的电路设计的部分选择。 使用排除部分的抽象版本，安全验证系统产生电路设计的第二电路模型，用于确定污染数据是否可以从电路设计内的第一位置到达第二位置。

公开(公告)号：US20150100933A1

公开(公告)日：2015-04-09

申请号：US14050309

申请日：2013-10-09

Applicant: Jasper Design Automation, Inc.

Inventor： Claudionor José Nunes Coelho, JR. ,  Chien-Liang Lin ,  Chung-Wah Norris Ip

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5081

Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Abstract translation: 查看器显示电路设计活动，显示信号，其对应的跟踪以及随时间变化的轨迹值。 在值显示上提供全局放大，缩小和缩放，以调整查看器中覆盖的时间间隔。 观看者内的轨迹的非线性操纵使得能够同时放大多个时间间隔的显示，并且缩小其他时间间隔的显示。 非线性操作可以在相同的显示区域内通过指定对应于选择电路的指定时间段的缩放组来执行。 每个缩放组可以独立于其它定时器周期进行缩放，以放大或缩小在指定时间段内发生的活动。 还可以提供行为列表。 选择行为会产生与行为相关联的信号和相应跟踪的单独信号列表，以增强调试。

公开(公告)号：US09460252B1

公开(公告)日：2016-10-04

申请号：US14250183

申请日：2014-04-10

Applicant: Jasper Design Automation, Inc.

Inventor： Asa Ben-Tzur ,  Ziyad Hanna

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F17/504

Abstract: Tools for ranking of generated properties are described. A plurality of circuit design properties are generated from a signal trace of the circuit design. A static analysis of the circuit design properties is performed against one or more circuit design constraints to determine whether the properties are true. Rankings for the circuit design properties are determined responsive to results of the static analysis. The ranking for a circuit design property represents a value of the circuit design property in validating correct functionality of the circuit design. At least some of the circuit design properties are presented in a user interface responsive to the rankings for the circuit design properties.

Abstract translation: 描述了生成属性排名的工具。 从电路设计的信号迹线产生多个电路设计特性。 根据一个或多个电路设计约束执行电路设计属性的静态分析，以确定属性是否为真。 响应于静态分析的结果确定电路设计属性的排名。 电路设计属性的排名表示电路设计特性的值，用于验证电路设计的正确功能。 至少一些电路设计属性在响应于电路设计属性的排名的用户界面中呈现。

公开(公告)号：US09158874B1

公开(公告)日：2015-10-13

申请号：US14073787

申请日：2013-11-06

Applicant: Jasper Design Automation, Inc.

Inventor： Rajeev K. Ranjan ,  Ross M. Weber ,  Habeeb A. Farah ,  Ziyad E. Hanna

IPC: G06F17/50

CPC classification number: G06F17/504 ,  G06F17/50 ,  G06F17/5022 ,  G06F17/5081

Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. A property defined for a circuit design is received, the property having a cone of influence in the circuit design corresponding to a portion of the circuit design capable of affecting the property. Bounded reachability analysis is performed for the circuit design against a set of cover items. The set of cover items are classified into classified cover items based on results of the reachability analysis. Coverage information is generated indicating an amount of formal verification coverage provided by the property. The coverage information is generated based on a first set of the classified cover items that correspond to the cone of influence of the property and that are reached within a particular bound during the reachability analysis.

Abstract translation: 一种用于电路设计验证的计算机实现的方法和非暂时性计算机可读介质。 接收为电路设计定义的属性，该属性在电路设计中具有与影响该性能的电路设计的一部分相对应的影响锥。 对一套封面项目进行电路设计的有界可达性分析。 根据可达性分析的结果，将一套封面项目分类为分类覆盖项目。 生成指示由属性提供的正式验证覆盖量的覆盖信息。 覆盖信息是基于对应于属性的影响锥度并且在可达性分析期间在特定边界内达到的分类覆盖项目的第一组生成的。

公开(公告)号：US20150100932A1

公开(公告)日：2015-04-09

申请号：US14046891

申请日：2013-10-04

Applicant: Jasper Design Automation, Inc.

Inventor： Claudionor José Nunes Coelho, JR. ,  Chien-Liang Lin ,  Chung-Wah Norris Ip

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5081

Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Abstract translation: 查看器显示电路设计活动，显示信号，其对应的跟踪以及随时间变化的轨迹值。 在值显示上提供全局放大，缩小和缩放，以调整查看器中覆盖的时间间隔。 观看者内的轨迹的非线性操纵使得能够同时放大多个时间间隔的显示，并且缩小其他时间间隔的显示。 非线性操作可以在相同的显示区域内通过指定对应于选择电路的指定时间段的缩放组来执行。 每个缩放组可以独立于其它定时器周期进行缩放，以放大或缩小在指定时间段内发生的活动。 还可以提供行为列表。 选择行为会产生与行为相关联的信号和相应跟踪的单独信号列表，以增强调试。

公开(公告)号：US08954904B1

公开(公告)日：2015-02-10

申请号：US13874388

申请日：2013-04-30

Applicant: Jasper Design Automation, Inc.

Inventor： Lawrence Loh ,  Barbara Jobstmann ,  Antonio Celso Caldeira, Jr. ,  Jamil R. Mazzawi

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022 ,  G06F17/504 ,  G06F2217/78

Abstract: A register transfer level (RTL) design is received which models a digital circuit in terms of the flow of digital signals. A power intent description is received which may include a description of power domains, identification of retention flops for each power domain, a list of isolation signals, and power switch definitions. A transformed RTL is produced accounting for functionality described in the power intent description. The transformed RTL includes flops designated as retention flops and non-retention flops. A retention flop module analyzes the flops to ensure that flops are properly designated as retention or non-retention flops. A verification module performs power aware sequential equivalence checking on various RTL and power intent descriptions to verify that RTL and power intent description outputs behave the same when accounting for power states.

Abstract translation: 接收到数字信号流的数字电路的寄存器传送电平（RTL）设计。 接收到功率意图描述，其可以包括功率域的描述，每个功率域的保持触发器的识别，隔离信号的列表和功率开关定义。 产生转换后的RTL，用于说明功率意图描述中描述的功能。 转换的RTL包括指定为保留触发器和非保留触发器的触发器。 保留触发器模块分析触发器以确保触发器被适当地指定为保留或非保留触发器。 验证模块对各种RTL和功率意图描述执行功率感知顺序等同性检查，以便在计算功率状态时验证RTL和功率意图描述输出的性能相同。

公开(公告)号：US09081927B2

公开(公告)日：2015-07-14

申请号：US14046891

申请日：2013-10-04

Applicant: Jasper Design Automation, Inc.

Inventor： Claudionor José Nunes Coelho, Jr. ,  Chien-Liang Lin ,  Chung-Wah Norris Ip

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5081

Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.

Abstract translation: 查看器显示电路设计活动，显示信号，其对应的跟踪以及随时间变化的轨迹值。 在值显示上提供全局放大，缩小和缩放，以调整查看器中覆盖的时间间隔。 观看者内的轨迹的非线性操纵使得能够同时放大多个时间间隔的显示，并且缩小其他时间间隔的显示。 非线性操作可以在相同的显示区域内通过指定对应于选择电路的指定时间段的缩放组来执行。 每个缩放组可以独立于其它定时器周期进行缩放，以放大或缩小在指定时间段内发生的活动。 还可以提供行为列表。 选择行为会产生与行为相关联的信号和相应跟踪的单独信号列表，以增强调试。

公开(公告)号：US20150095862A1

公开(公告)日：2015-04-02

申请号：US14044681

申请日：2013-10-02

Applicant: Jasper Design Automation, Inc.

Inventor： Chung-Wah Norris Ip ,  Chien-Liang Lin

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F2217/06

Abstract: A first waveform for a circuit design is received. The first waveform includes at least an actual value of a signal of the circuit design at one or more clock cycles. A user input for a cursor is received, and a signal wave overlay is displayed on the first waveform having an appearance corresponding to a location of the cursor. The signal wave overlay indicates a desired value of the signal at one or more clock cycles that is different than the actual value of the signal in the one or more clock cycles. Based on the desired value of the signal indicated by the signal wave overlay, a visualization constraint for the circuit design is generated. The visualization constraint is used to generate a second waveform, where the visualization constraint restricts the second waveform.

Abstract translation: 接收电路设计的第一波形。 第一波形包括至少一个或多个时钟周期的电路设计的信号的实际值。 接收用于光标的用户输入，并且在具有与光标位置相对应的外观的第一波形上显示信号波叠加。 信号波叠加指示在一个或多个时钟周期的信号的期望值，其不同于一个或多个时钟周期中的信号的实际值。 基于由信号波叠加指示的信号的期望值，产生电路设计的可视化约束。 可视化约束用于生成第二波形，其中可视化约束限制第二波形。

公开(公告)号：US08826201B1

公开(公告)日：2014-09-02

申请号：US13826801

申请日：2013-03-14

Applicant: Jasper Design Automation, Inc.

Inventor： Ziyad E. Hanna ,  Per Anders M. Franzén ,  Ross M. Weber ,  Habeeb A. Farah ,  Rajeev K. Ranjan

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/504

Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

Abstract translation: 一种用于电路设计验证的计算机实现的方法和非暂时性计算机可读介质。 对电路设计进行正式验证，以证明电路设计的属性的正确性。 电路设计具有代表电路设计能够影响该特性的信号的一部分的影响锥。 识别电路设计的核心，防爆核心是足以证明属性正确性的影响力的一部分。 产生一个覆盖度量，其指示由基于电路设计的验证核心的属性提供的形式验证覆盖水平。

公开(公告)号：US09104824B1

公开(公告)日：2015-08-11

申请号：US13874398

申请日：2013-04-30

Applicant: Jasper Design Automation, Inc.

Inventor： Lawrence Loh ,  Barbara Jobstmann ,  Antonio Celso Caldeira, Jr. ,  Jamil R. Mazzawi

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5081 ,  G06F2217/78

Abstract: A register transfer level (RTL) design is received which models a digital circuit in terms of the flow of digital signals. A power intent description is received which may include a description of power domains, identification of retention flops for each power domain, a list of isolation signals, and power switch definitions. A transformed RTL is produced accounting for functionality described in the power intent description. The transformed RTL includes flops designated as retention flops and non-retention flops. A retention flop module analyzes the flops to ensure that flops are properly designated as retention or non-retention flops. A verification module performs power aware sequential equivalence checking on various RTL and power intent descriptions to verify that RTL and power intent description outputs behave the same when accounting for power states.

Abstract translation: 接收到数字信号流的数字电路的寄存器传送电平（RTL）设计。 接收到功率意图描述，其可以包括功率域的描述，每个功率域的保持触发器的标识，隔离信号的列表和功率开关定义。 产生转换后的RTL，用于说明功率意图描述中描述的功能。 转换的RTL包括指定为保留触发器和非保留触发器的触发器。 保留触发器模块分析触发器以确保触发器被适当地指定为保留或非保留触发器。 验证模块对各种RTL和功率意图描述执行功率感知顺序等同性检查，以便在计算功率状态时验证RTL和功率意图描述输出的性能相同。