发明申请
- 专利标题： High-Speed Receiver Architecture
- 专利标题（中）： 高速接收机架构
-
申请号： US14480085申请日： 2014-09-08
-
公开(公告)号： US20150098710A1公开(公告)日： 2015-04-09
- 发明人: Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Hugo Santiago Carrer , Mario Rafael Hueda , German Cesar Augusto Luna , Carl Grace
- 申请人： ClariPhy Communications. Inc.
- 主分类号： H04B10/40
- IPC分类号： H04B10/40
摘要：
A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
公开/授权文献
- US09531475B2 High-speed receiver architecture 公开/授权日：2016-12-27
信息查询
