Invention Application
US20150149725A1 MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS 有权
用于执行原子二进制翻译的多线程系统

  • Patent Title: MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS
  • Patent Title (中): 用于执行原子二进制翻译的多线程系统
  • Application No.: US14088446
    Application Date: 2013-11-25
  • Publication No.: US20150149725A1
    Publication Date: 2015-05-28
  • Inventor: Ashish MathurSandeep Jain
  • Applicant: Ashish MathurSandeep Jain
  • Main IPC: G06F12/08
  • IPC: G06F12/08
MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS
Abstract:
A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.
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