利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.019 秒)

    Multi-threaded system for performing atomic binary translations
    1.
    发明授权
    Multi-threaded system for performing atomic binary translations 有权
    用于执行原子二进制翻译的多线程系统

    公开(公告)号：US09053035B1

    公开(公告)日：2015-06-09

    申请号：US14088446

    申请日：2013-11-25

    申请人： Ashish Mathur ,  Sandeep Jain

    发明人： Ashish Mathur ,  Sandeep Jain

    IPC分类号： G06F12/02 ,  G06F12/08

    CPC分类号： G06F9/3004 ,  G06F8/45 ,  G06F8/52 ,  G06F9/45558

    摘要： A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

    摘要翻译： 多线程二进制翻译系统通过线程执行原子操作，这样的操作包括处理加载链接指令和存储条件指令。 存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。 条件是：负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同，保留标志指示线程具有有效预留，以及负载存储的数据副本 链接指令与存储在存储条件共享存储器地址中的数据相同。

    MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS
    2.
    发明申请
    MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS 有权
    用于执行原子二进制翻译的多线程系统

    公开(公告)号：US20150149725A1

    公开(公告)日：2015-05-28

    申请号：US14088446

    申请日：2013-11-25

    申请人： Ashish Mathur ,  Sandeep Jain

    发明人： Ashish Mathur ,  Sandeep Jain

    IPC分类号： G06F12/08

    CPC分类号： G06F9/3004 ,  G06F8/45 ,  G06F8/52 ,  G06F9/45558

    摘要： A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

    摘要翻译： 多线程二进制翻译系统通过线程执行原子操作，这样的操作包括处理加载链接指令和存储条件指令。 存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。 条件是：负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同，保留标志指示线程具有有效预留，以及负载存储的数据副本 链接指令与存储在存储条件共享存储器地址中的数据相同。

    Increasing precision in multi-stage processing of digital signals
    8.
    发明授权
    Increasing precision in multi-stage processing of digital signals 失效

    公开(公告)号：US06996597B2

    公开(公告)日：2006-02-07

    申请号：US10092927

    申请日：2002-03-06

    申请人： Ashish Mathur ,  Srinivasan Gopalaswamy ,  Pradeep Jain

    发明人： Ashish Mathur ,  Srinivasan Gopalaswamy ,  Pradeep Jain

    IPC分类号： G06F7/38

    CPC分类号： H04L27/2628

    摘要： Precision of multi-stage digital signal processing is increased by preserving least significant bits of one or more output samples of a particular processing stage, having finite word widths, while avoiding the loss of most significant bits. The technique is applicable to one or more stages of multi-stage digital signal processing, thereby increasing precision therein and the signal-to-noise ratio. A plurality of output samples are calculated using a plurality of input samples, and the dynamic range of one or more of the output samples is decreased if the output sample can be represented in a smaller dynamic range without losing a significant bit. The input samples of a particular stage, obtained from the output samples of a previous stage, may further be normalized so that the input samples are represented in the same dynamic range before being processed.

    Method and system for estimating power consumption of integrated circuit design
    10.
    发明授权
    Method and system for estimating power consumption of integrated circuit design 有权
    集成电路设计功耗估算方法及系统

    公开(公告)号：US07971082B2

    公开(公告)日：2011-06-28

    申请号：US12013478

    申请日：2008-01-14

    申请人： Ashish Mathur ,  Vijay Bhargava

    发明人： Ashish Mathur ,  Vijay Bhargava

    IPC分类号： G06F1/32

    CPC分类号： G06F9/3869

    摘要： A method and system for estimating power consumption for at least one Intellectual Property (IP) block in an integrated circuit (IC) design includes identifying at least one port in the at least one IP block. The at least one port is associated with at least one operation. A sequence of micro-operations of the at least one operation is identified. The sequence of micro-operations constitutes an operation pipeline. A set of micro-operations per cycle in the operation pipeline and energy per cycle of each cycle of the operation pipeline, based on the set of micro-operations per cycle by using one or more of, an idle energy value, a micro-operation isolated energy (MIE) value, an overlap energy (OE) value, and a micro-operation overlap energy (MOE) value, are determined. Then the power consumption of the at least one IP block is determined using the energy per cycle of each cycle of the operation pipeline.

    摘要翻译： 用于估计集成电路（IC）设计中的至少一个知识产权（IP）块的功率消耗的方法和系统包括识别所述至少一个IP块中的至少一个端口。 至少一个端口与至少一个操作相关联。 识别至少一个操作的一系列微操作。 微操作的顺序构成操作流程。 基于通过使用空闲能量值，微操作的每个周期的微操作的集合，在操作流水线中的每个周期的一组微操作和每个操作流水线的每个周期的每个周期的能量 分离能量（MIE）值，重叠能量（OE）值和微操作重叠能量（MOE）值。 然后，使用运行管线的每个循环的每循环的能量确定至少一个IP块的功率消耗。