Invention Application
- Patent Title: MULTIPLY ADDER
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Application No.: US14566981Application Date: 2014-12-11
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Publication No.: US20150199173A1Publication Date: 2015-07-16
- Inventor: David Raymond LUTZ , Neil BURGESS
- Applicant: ARM LIMITED
- Priority: GB1400644.9 20140115
- Main IPC: G06F7/544
- IPC: G06F7/544 ; G06F5/01

Abstract:
A floating point multiply add circuit 24 includes a multiplier 26 and an adder 28. The input operands A, B and C together with the result value all have a normal exponent value range, such as a range consistent with the IEEE Standard 754. The product value which is passed from the multiplier 26 to the adder 28 as an extended exponent value range that extents lower than the normal exponent value range. Shifters 48, 50 within the adder can take account of the extended exponent value range of the product as necessary in order to bring the result value back into the normal exponent value range.
Public/Granted literature
- US09696964B2 Multiply adder Public/Granted day:2017-07-04
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