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公开(公告)号：US20170293467A1
公开(公告)日：2017-10-12
申请号：US15093947
申请日：2016-04-08
申请人： ARM LIMITED
CPC分类号： G06F5/015 , G06F7/483 , G06F9/30014 , G06F9/30025 , H03M7/24
摘要： A data processing system 2 includes instruction decoder circuitry 12 responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry 28 performs a right shift upon at least part of the input number and left shifting circuitry 32 performs a left shift of at least part of the input number. Selection circuitry 38 serves to select one of the right shifted number and the left shifted number as a selected shifted number which forms at least part of the output number which is generated.
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2.发明申请EXCEPTION GENERATION WHEN GENERATING A RESULT VALUE WITH PROGRAMMABLE BIT SIGNIFICANCE 有权当产生具有可编程位意义的结果值时的异常生成公开(公告)号：US20160124714A1
公开(公告)日：2016-05-05
申请号：US14582978
申请日：2014-12-24
申请人： ARM Limited
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system performs processing operations upon input operand(s) having a programmable bit significance. Exception generating circuitry generates exception indications representing exceptions such as overflow, underflow and inexact in respect of a result value having the programmable bit significance.
摘要翻译： 数据处理系统对具有可编程位有效位的输入操作数执行处理操作。 异常产生电路产生异常指示，表示异常，例如溢出，下溢和不精确的具有可编程位重要性的结果值。
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公开(公告)号：US20160055888A1
公开(公告)日：2016-02-25
申请号：US14933402
申请日：2015-11-05
申请人： ARM Limited
发明人： David Raymond LUTZ , Neil BURGESS
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F5/01 , G06F7/49921 , G06F9/30018 , G06F9/30032 , G11C7/1084
摘要： Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results.
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公开(公告)号：US20150199173A1
公开(公告)日：2015-07-16
申请号：US14566981
申请日：2014-12-11
申请人： ARM LIMITED
发明人： David Raymond LUTZ , Neil BURGESS
CPC分类号： G06F7/5443 , G06F7/483
摘要： A floating point multiply add circuit 24 includes a multiplier 26 and an adder 28. The input operands A, B and C together with the result value all have a normal exponent value range, such as a range consistent with the IEEE Standard 754. The product value which is passed from the multiplier 26 to the adder 28 as an extended exponent value range that extents lower than the normal exponent value range. Shifters 48, 50 within the adder can take account of the extended exponent value range of the product as necessary in order to bring the result value back into the normal exponent value range.
摘要翻译： 浮点乘法加法电路24包括乘法器26和加法器28.输入操作数A，B和C以及结果值都具有正常的指数值范围，例如与IEEE标准754一致的范围。该产品 该值从乘法器26传递到加法器28作为扩展指数值范围，其范围低于正常指数值范围。 加法器内的移位器48,50可以根据需要考虑乘积的扩展指数值范围，以使结果值返回正常指数值范围。
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公开(公告)号：US20150012724A1
公开(公告)日：2015-01-08
申请号：US13936576
申请日：2013-07-08
申请人： ARM LIMITED
发明人： David Raymond LUTZ , Neil BURGESS
IPC分类号： G06F9/38
CPC分类号： G06F9/3887 , G06F9/30014 , G06F9/30032 , G06F9/30036
摘要： A data processing apparatus has permutation circuitry for performing a permutation operation for changing a data element size or data element positioning of at least one source operand to generate first and second SIMD operands, and SIMD processing circuitry for performing a SIMD operation on the first and second SIMD operands. In response to a first SIMD instruction requiring a permutation operation, the instruction decoder controls the permutation circuitry to perform the permutation operation to generate the first and second SIMD operands and then controls the SIMD processing circuitry to perform the SIMD operation using these operands. In response to a second SIMD instruction not requiring a permutation operation, the instruction decoder controls the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the instruction, without passing them via the permutation circuitry.
摘要翻译： 数据处理装置具有排列电路，用于执行用于改变至少一个源操作数的数据元素大小或数据元素定位以产生第一和第二SIMD操作数的置换操作，以及用于在第一和第二操作数上执行SIMD操作的SIMD处理电路 SIMD操作数。 响应于需要置换操作的第一SIMD指令，指令解码器控制置换电路以执行置换操作以产生第一和第二SIMD操作数，然后控制SIMD处理电路以使用这些操作数执行SIMD操作。 响应于不需要置换操作的第二SIMD指令，指令解码器控制SIMD处理电路，使用由指令识别的第一和第二SIMD操作数来执行SIMD操作，而不通过置换电路。
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公开(公告)号：US20210026600A1
公开(公告)日：2021-01-28
申请号：US16521740
申请日：2019-07-25
申请人： Arm Limited
摘要： An apparatus and method are provided for performing an index operation. The apparatus has vector processing circuitry to perform an index operation in each of a plurality of lanes of parallel processing. The index operation requires an index value opm to be multiplied by a multiplier value e to produce a multiplication result. The number of lanes of parallel processing is dependent on a specified element size, and the multiplier value is different, but known, for each lane of parallel processing. The vector processing circuitry comprises mapping circuitry to perform, within each lane, mapping operations on the index value opm in order to generate a plurality of intermediate input values. The plurality of intermediate input values are such that the addition of the plurality of intermediate input values produces the multiplication result. Within each lane the mapping operations are determined by the multiplier value used for that lane. The vector processing circuitry also has vector adder circuitry to perform, within each lane, an addition of at least the plurality of intermediate input values, in order to produce a result vector providing a result value for the index operation performed in each lane. This provides a high performance, low latency, technique for vectorising index operations.
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公开(公告)号：US20200310796A1
公开(公告)日：2020-10-01
申请号：US16368930
申请日：2019-03-29
申请人： Arm Limited
IPC分类号： G06F9/30
摘要： An apparatus has processing circuitry to perform, in response to decoding of an iterative-operation instruction by the instruction decoder, an iterative operation comprising at least two iterations of processing where one iteration depends on an operand generated in a previous iteration. Preliminary information generating circuitry performs a preliminary portion of processing for a given iteration to generate preliminary information. Result generating circuitry performs a remaining portion of processing for the given iteration, to generate a result value using the preliminary information. Forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation, for iterations other than the final iteration. The preliminary information generating circuitry starts performing the preliminary portion for the next iteration in parallel with the result generating circuitry completing the remaining portion for the current iteration, to improve performance.
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公开(公告)号：US20200257499A1
公开(公告)日：2020-08-13
申请号：US16268692
申请日：2019-02-06
申请人： Arm Limited
摘要： Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.
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公开(公告)号：US20180329682A1
公开(公告)日：2018-11-15
申请号：US15593574
申请日：2017-05-12
申请人： ARM Limited
发明人： David Raymond LUTZ
摘要： A data processing apparatus includes difference circuitry that calculates a difference between exponents of a first floating-point operand and a second floating-point operand. Shift circuitry generates a fractional string by shifting fractional bits of a selected operand of the first floating-point operand and the second floating-point operand based on the difference. Logic circuitry generates an integer-bit string representing an integer-bit of the selected operand having been shifted based on the difference. Combining circuitry combines the fractional string and the integer-bit string to produce a significand string representing the selected operand having been shifted based on the difference. The logic circuitry generates the integer-bit string using operations other than shifting.
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10.发明申请公开(公告)号：US20180285076A1
公开(公告)日：2018-10-04
申请号：US15473841
申请日：2017-03-30
申请人： ARM Limited
摘要： An apparatus and method are provided for estimating a shift amount when employing processing circuitry to perform a subtraction operation to subtract a second significand value of a second floating-point operand from a first significand value of a first floating-point operand in order to generate a difference value. Shift estimation circuitry then determines an estimated shift amount to be applied to the difference value. The shift estimation circuitry comprises significand analysis circuitry to generate, from analysis of the significand values of the two floating-point operands, a first bit string identifying a most significant bit position within the difference value that is predicted to have its bit set to a determined value. In parallel, shift limiting circuitry generates from an exponent value a second bit string identifying a shift limit bit position. The shift limiting circuitry has computation circuitry to perform, for each bit position in at least a subset of bit positions of the second bit string, an associated computation using bits of the exponent value to determine a value for that bit position within the second bit string. The associated computation is different for different bit positions. Combining circuitry then generates a combined bit string from the first and second bit strings, and shift determination circuitry determines the estimated shift amount from the combined bit string.
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