Invention Application
- Patent Title: Methods of Forming Memory Arrays and Semiconductor Constructions
- Patent Title (中): 形成记忆阵列和半导体结构的方法
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Application No.: US14569337Application Date: 2014-12-12
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Publication No.: US20150206886A1Publication Date: 2015-07-23
- Inventor: Jaydip Guha , Shyam Surthi
- Applicant: Micron Technology, Inc.
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/04 ; H01L21/324 ; H01L21/02 ; H01L21/265 ; H01L29/66 ; H01L29/16

Abstract:
Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
Public/Granted literature
- US09230968B2 Methods of forming memory arrays and semiconductor constructions Public/Granted day:2016-01-05
Information query
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