公开(公告)号：US11729982B2

公开(公告)日：2023-08-15

申请号：US17507660

申请日：2021-10-21

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill

IPC分类号： H01L27/11582 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC分类号： H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

摘要： Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.

公开(公告)号：US11672118B2

公开(公告)日：2023-06-06

申请号：US17013047

申请日：2020-09-04

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC分类号： H01L27/11582

CPC分类号： H01L27/11582

摘要： An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US11189629B2

公开(公告)日：2021-11-30

申请号：US16863120

申请日：2020-04-30

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

摘要： Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.

公开(公告)号：US20210335817A1

公开(公告)日：2021-10-28

申请号：US17369605

申请日：2021-07-07

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11107830B2

公开(公告)日：2021-08-31

申请号：US16548267

申请日：2019-08-22

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Francois H Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  H01L29/792

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11081498B2

公开(公告)日：2021-08-03

申请号：US16548120

申请日：2019-08-22

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill

IPC分类号： H01L27/11582 ,  H01L45/00 ,  H01L21/768 ,  G11C16/08

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11037956B2

公开(公告)日：2021-06-15

申请号：US16988548

申请日：2020-08-07

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  G11C16/08

摘要： Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11031414B2

公开(公告)日：2021-06-08

申请号：US16434052

申请日：2019-06-06

申请人： Micron Technology, Inc.

发明人： John D. Hopkins ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  G11C5/06 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.

公开(公告)号：US20210143171A1

公开(公告)日：2021-05-13

申请号：US16681200

申请日：2019-11-12

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

摘要： Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20180226406A1

公开(公告)日：2018-08-09

申请号：US15942938

申请日：2018-04-02

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Suraj Mathew

IPC分类号： H01L27/105 ,  H01L21/768 ,  H01L21/74 ,  H01L27/108

CPC分类号： H01L27/1052 ,  H01L21/743 ,  H01L21/76897 ,  H01L27/10885

摘要： Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.