Invention Application
- Patent Title: METHODS FOR REDUCING MEMORY SPACE IN SEQUENTIAL OPERATIONS USING DIRECTED ACYCLIC GRAPHS
- Patent Title (中): 使用方向图的顺序操作减少记忆空间的方法
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Application No.: US14165789Application Date: 2014-01-28
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Publication No.: US20150212933A1Publication Date: 2015-07-30
- Inventor: Vinod Grover , Mahesh Ravishankar
- Applicant: Nvidia Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Nvidia Corporation
- Current Assignee: Nvidia Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06T1/60

Abstract:
Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data.
Public/Granted literature
- US09563933B2 Methods for reducing memory space in sequential operations using directed acyclic graphs Public/Granted day:2017-02-07
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