Invention Application
- Patent Title: CLOCK GENERATION SYSTEM WITH DYNAMIC DISTRIBUTION BYPASS MODE
- Patent Title (中): 具有动态分配旁路模式的时钟发生系统
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Application No.: US14126005Application Date: 2013-06-28
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Publication No.: US20150214959A1Publication Date: 2015-07-30
- Inventor: Allan Feldman , Nasser Kurd , Mark Neidengard , Vaughn Grossnickle , Praveen Mosalikanti
- Applicant: INTEL CORPORATION
- International Application: PCT/US13/48580 WO 20130628
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/083
Abstract:
In some embodiments, a tight loop mode is provided is which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.
Public/Granted literature
- US09450589B2 Clock generation system with dynamic distribution bypass mode Public/Granted day:2016-09-20
Information query
