A nonvolatile memory device includes a word line, four or more bit lines, three or more MIS transistors having gate nodes thereof connected to the word line, the N-th (N: positive integer) one of the MIS transistors having two source/drain nodes thereof connected to the N-th and N+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the N-th and N+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the N+1-th one of the bit lines to a fixed potential, for any numerical number N selected to detect single-bit data stored in the N-th and N+1-th ones of the MIS transistors.