A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.