公开(公告)号：US20160019145A1

公开(公告)日：2016-01-21

申请号：US14766911

申请日：2013-10-15

Applicant: HITACHI, LTD.

Inventor： Yoshifumi MIMATA ,  Yuko MATSUI ,  Shintaro KUDO

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/06 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0868 ,  G06F2212/50

Abstract: A receiving controller which receives a read request out of first and second storage controllers transfers the read request to an associated controller which is associated with a read source storage area out of the first and second storage controllers when the receiving controller is not the associated controller. It is however the receiving controller that reads the read-target data from a read source storage device, writes the read-target data to a cache memory of the receiving controller, and transmits the read-target data written in the cache memory of the receiving controller to a host apparatus.

Abstract translation: 当接收控制器不是相关联的控制器时，从第一和第二存储控制器接收读取请求的接收控制器将读取请求传送到与第一和第二存储控制器中的读取源存储区域相关联的关联控制器。 然而，接收控制器从读取源存储设备读取读取目标数据，将读取目标数据写入接收控制器的高速缓冲存储器，并将写入高速缓冲存储器中的读取目标数据发送给接收 控制器到主机设备。

公开(公告)号：US20160342512A1

公开(公告)日：2016-11-24

申请号：US14424625

申请日：2014-01-21

Applicant: HITACHI, LTD.

Inventor： Yuki SAKASHITA ,  Shintaro KUDO ,  Yoshihiro YOSHII ,  Yusuke NONAKA

IPC: G06F12/0804 ,  G06F12/0866

CPC classification number: G06F12/0804 ,  G06F12/0866 ,  G06F12/0868 ,  G06F2212/1008 ,  G06F2212/281 ,  G06F2212/313

Abstract: The invention provides a technique for improving processing performance of I/O commands in a storage system in which ownership of each LU is introduced. The storage system includes: a disk device having storage regions that are managed as a plurality of logical units; a plurality of processors that process read commands to the disk device; and a cache that the processors can use to process the read commands. An owner processor that is in charge of processing to each logical unit is allocated to each logical unit. When decision is made that dirty data is not present in the cache in a target region of the read command, there are a case where the owner processor of a logical unit that includes the target region processes the read command, and a case where a non-owner processor, as the processor other than the owner processor, processes the read command.

Abstract translation: 本发明提供一种用于提高在其中引入了每个LU的所有权的存储系统中的I / O命令的处理性能的技术。 存储系统包括：具有作为多个逻辑单元管理的存储区域的磁盘设备; 将读取命令处理到所述磁盘设备的多个处理器; 以及处理器可用于处理读取命令的高速缓存。 负责处理每个逻辑单元的所有者处理器被分配给每个逻辑单元。 当在读取命令的目标区域中的高速缓存中不存在脏数据时，存在包括目标区域的逻辑单元的所有者处理器处理读取命令的情况， 作为除所有者处理器之外的处理器的所有者处理器处理读取命令。

公开(公告)号：US20160246660A1

公开(公告)日：2016-08-25

申请号：US15027830

申请日：2013-10-24

Applicant: HITACHI, LTD.

Inventor： Yusuke NISHIHARA ,  Yuko MATSUI ,  Shintaro KUDO

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/079 ,  G06F3/06 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0689 ,  G06F11/0727 ,  G06F11/076 ,  G06F13/00 ,  G06F13/14 ,  G06F13/385

Abstract: Provided is a storage system which is connected to a host computer and whereby data is read and written. The storage system comprises: a storage device which stores the data; and a storage controller wherein an error is detected by one of a plurality of first sections which are sections upon a transfer path of the data with respect to the storage device in a full check mode, an error is detected by one of second sections which are fewer than the first sections in a regular mode, and a switch is made to the full check mode when the error is detected in the regular mode.

Abstract translation: 提供了连接到主计算机并且读取和写入数据的存储系统。 存储系统包括：存储数据的存储装置; 以及存储控制器，其中，以完全检查模式，在数据相对于存储装置的传送路径上的部分的多个第一部分中的一个检测到错误，由第二部分之一检测到错误 少于常规模式中的第一部分，并且当在常规模式中检测到错误时，切换到完全检查模式。

公开(公告)号：US20170075816A1

公开(公告)日：2017-03-16

申请号：US15125313

申请日：2014-04-24

Applicant: HITACHI, LTD.

Inventor： Naoya OKADA ,  Masanori TAKADA ,  Shintaro KUDO ,  Yusuke NONAKA ,  Tadashi TAKEUCHI

IPC: G06F12/1009 ,  G06F3/06 ,  G06F13/16 ,  G06F12/109

CPC classification number: G06F12/1009 ,  G06F3/06 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0683 ,  G06F12/109 ,  G06F12/1441 ,  G06F13/14 ,  G06F13/1668 ,  G06F21/79 ,  G06F2221/2141

Abstract: A control apparatus, in a storage system, accesses a specific storage area in a shared memory by designating a fixed virtual address, even when a capacity of the shared memory in the storage system changes. A space of a physical address indicating a storage area in a plurality of memories in a self-control-subsystem of two control-subsystems and a space of a physical address indicating a storage area in the plurality of memories in the other-control-subsystem are associated with a space of a virtual address used by each of a processor and an input/output device in the self-control-subsystem. Upon receiving data transferred from the other-control-subsystem to the self-control-subsystem, a relay device translates a virtual address indicating a transfer destination of the data designated by the other-control-subsystem into a virtual address in the self-control-subsystem based on an offset determined in advance, and transfers the data to the translated virtual address.

Abstract translation: 存储系统中的控制装置即使当存储系统中的共享存储器的容量改变时，通过指定固定的虚拟地址来访问共享存储器中的特定存储区域。 指示两个控制子系统的自控子系统中的多个存储器中的存储区域的物理地址的空间和指示另一个控制子系统中的多个存储器中的存储区域的物理地址的空间 与自控子系统中的处理器和输入/输出设备中的每一个使用的虚拟地址的空间相关联。 在接收到从其他控制子系统传送到自控子系统的数据时，中继装置将指示由另一控制子系统指定的数据的传送目的地的虚拟地址转换为自控制中的虚拟地址 - 基于预先确定的偏移的子系统，并将数据传送到转换的虚拟地址。

公开(公告)号：US20150370713A1

公开(公告)日：2015-12-24

申请号：US14765442

申请日：2013-10-09

Applicant: HITACHI, LTD.

Inventor： Noboru MORISHITA ,  Shintaro KUDO ,  Yusuke NONAKA ,  Akira YAMAMOTO

IPC: G06F12/08

CPC classification number: G06F12/0868 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F11/14 ,  G06F12/0895 ,  G06F13/10 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/283 ,  G06F2212/313

Abstract: In a storage system, first and second controllers have respective first and second buffer and cache areas. The first controller stores write data in accordance with a write request in the first cache area without involving the first buffer area and to transfer the stored write data to the second cache area without involving the second buffer area. The first controller is configured to determine which of the first and second cache areas is to be used as a copy source and to be used as a copy destination depending on whether the storing of the first write data in the first cache area had been successful or on whether the transfer of the write data from the first cache area to the second controller had been successful, and by copying data from the copy source to the copy destination, recovers data in an area related to a transfer failure.

Abstract translation: 在存储系统中，第一和第二控制器具有相应的第一和第二缓冲器和缓存区域。 第一控制器将写入数据按照第一高速缓存区域中的写入请求存储而不涉及​​第一缓冲区域，并将存储的写入数据传送到第二高速缓存区域而不涉及第二缓冲区域。 第一控制器被配置为根据第一高速缓存区域中的第一写入数据的存储是否已经成功而确定将第一和第二高速缓存区域中的哪一个用作复制源并被用作复制目的地，或者 关于从第一高速缓存区域到第二控制器的写入数据的传送是否已经成功，并且通过将数据从复制源复制到复制目的地，恢复与传输失败相关的区域中的数据。

公开(公告)号：US20150317093A1

公开(公告)日：2015-11-05

申请号：US14762039

申请日：2013-12-24

Applicant: HITACHI, LTD.

Inventor： Naoya OKADA ,  Yusuke NONAKA ,  Akihiko ARAKI ,  Shintaro KUDO ,  Makio MIZUNO

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0619 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0868 ,  G06F12/0875 ,  G06F12/0893 ,  G06F2212/222 ,  G06F2212/2228 ,  Y02D10/13

Abstract: A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.

Abstract translation: 存储控制器具有处理器，耦合到处理器并临时存储数据的易失性第一高速缓冲存储器，耦合到微处理器并临时存储数据的非易失性第二高速缓冲存储器，以及被配置为提供电气的电池 当发生停电时，至少将处理器和第一高速缓存存储器供电。 第二高速缓冲存储器包括用于存储不存储在存储装置中的数据的脏数据区域和除脏数据区域以外的剩余区域的脏数据区域。 当发生停电时，处理器将存储在第一高速缓冲存储器中的全部或一部分数据作为目标数据存储在第二高速缓冲存储器的剩余区域中。