According to example embodiments, a nonvolatile memory device includes a lower filling insulating layer covering a peripheral logic structure on a substrate, a horizontal semiconductor layer on the lower filling insulating layer, and a three-dimensional memory cell array including a plurality of memory blocks on the horizontal semiconductor layer. The horizontal semiconductor layer includes a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions. Each of the memory blocks includes sub-blocks on corresponding ones of the well regions. The non-volatile memory device is configured to perform an erase operation in units of the sub-blocks. The non-volatile memory device is configured to independently apply an erase voltage to a selected one of the well regions during the erase operation.