A system for reduced-rate predictive DFE. In one embodiment a plurality of sampler-multiplexer blocks, each including two samplers and a multiplexer-latch, controlled by a multi-phase clock, sample the received analog signal one at a time, and the output of each multiplexer-latch, which may represent the value of the last received bit, is used to control the select input of another multiplexer-latch, so that the other multiplexer-latch selects the appropriate one of two samplers, each applying a different correction to the received analog signal before sampling. Each multiplexer-latch is a clocked element that tracks the data input when the signal at its clock input has a first logic level and retains its output state when its clock input has another (i.e., a second) logic level.