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公开(公告)号：US12015423B2
公开(公告)日：2024-06-18
申请号：US18329429
申请日：2023-06-05
发明人： Aliazam Abbasfar , Amir Amirkhany
CPC分类号： H03M13/11 , H03M13/356 , H04L1/0041 , H04L1/007 , H04L1/0086
摘要： A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.
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公开(公告)号：US11632127B2
公开(公告)日：2023-04-18
申请号：US17506481
申请日：2021-10-20
发明人： Aliazam Abbasfar , Amir Amirkhany
摘要： A method of encoding input data includes dividing the input data into a plurality of data packets, an input packet of the plurality of data packets including a plurality of digits in a first base system, base-converting the input packet from the first base system to generate a base-converted packet including a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system, and incrementing the converted digits to generate a coded packet for transmission through a communication channel.
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公开(公告)号：US20220303110A1
公开(公告)日：2022-09-22
申请号：US17508898
申请日：2021-10-22
发明人： Gaurav Malhotra , Amir Amirkhany , Jalil Kamali
摘要： A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.
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公开(公告)号：US11081064B1
公开(公告)日：2021-08-03
申请号：US16869546
申请日：2020-05-07
发明人： Amir Amirkhany , Younghoon Song , Ranick Ng
IPC分类号： G09G3/3291 , H03M1/66 , H03F3/45
摘要： A display compensation circuit includes a driver circuit including a digital-to-analog converter (DAC), the driver circuit configured to drive pixels of a display panel; and a compensation circuit including a current-mode sensing circuit and a reference current generator circuit, the compensation circuit configured to determine a value to compensate for pixel variations across the display panel, the reference current generator circuit configured to generate a reference current using the DAC of the driver circuit.
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公开(公告)号：US20210217367A1
公开(公告)日：2021-07-15
申请号：US16869546
申请日：2020-05-07
发明人： Amir Amirkhany , Younghoon Song , Ranick Ng
IPC分类号： G09G3/3291 , H03M1/66
摘要： A display compensation circuit includes a driver circuit including a digital-to-analog converter (DAC), the driver circuit configured to drive pixels of a display panel; and a compensation circuit including a current-mode sensing circuit and a reference current generator circuit, the compensation circuit configured to determine a value to compensate for pixel variations across the display panel, the reference current generator circuit configured to generate a reference current using the DAC of the driver circuit.
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公开(公告)号：US20200136736A1
公开(公告)日：2020-04-30
申请号：US16275193
申请日：2019-02-13
发明人： Michael Wang , Amir Amirkhany
IPC分类号： H04J3/06
摘要： A system for word alignment. In some embodiments, the system includes a deserializer circuit, an alignment detection circuit, and a clock generator circuit. The clock generator circuit has a plurality of enable outputs connected to a plurality of enable inputs of the deserializer circuit, and a plurality of clock outputs connected to a plurality of clock inputs of the deserializer circuit. The alignment detection circuit is configured to detect a coarse word alignment; and, in response to detecting the coarse word alignment, to cause a reset of the clock generator circuit.
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公开(公告)号：US10411593B1
公开(公告)日：2019-09-10
申请号：US16109645
申请日：2018-08-22
发明人： Valentin Abramzon , Amir Amirkhany , Anup P. Jose
摘要： A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.
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8.发明授权Adaptive cyclic offset cancellation for the receiver front-end of high-speed serial links 有权高速串行接口接收机前端的自适应循环偏移消除公开(公告)号：US09571311B2
公开(公告)日：2017-02-14
申请号：US14944143
申请日：2015-11-17
CPC分类号： H04L25/061 , H04L25/028 , H04L25/0292 , H04L25/03057 , H04L27/0002
摘要： A receiver for a serial link. The receiver has an analog input configured to receive a received signal and includes a first front end comprising a first sampler configured to sample a signal at an input of the first front end, and a first correction circuit configured to add a first correction to the signal at the input of the first front end, the first correction including a first offset correction. The offset correction is updated by a modified sign-sign least mean squares method.
摘要翻译： 串行链接的接收器。 接收器具有被配置为接收接收信号的模拟输入，并且包括第一前端，其包括被配置为在第一前端的输入端采样信号的第一采样器，以及第一校正电路，其被配置为向信号添加第一校正 在第一前端的输入处，第一校正包括第一偏移校正。 通过改进的符号最小均方法更新偏移校正。
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公开(公告)号：US09536495B2
公开(公告)日：2017-01-03
申请号：US14594004
申请日：2015-01-09
发明人： Amir Amirkhany , Wei Xiong
CPC分类号： G09G5/006 , G09G3/20 , G09G3/2096 , G09G3/3266 , G09G3/3674 , G09G5/005 , G09G2310/027 , G09G2310/0286 , G09G2310/0297 , G09G2310/08 , G09G2352/00 , G09G2370/00 , G09G2370/08 , H04J3/08 , H04L25/0262 , H04L25/0264
摘要： A system for transmitting data from a timing controller (TCON) to several source driver integrated circuits (SICs) in a display. The system is suitable for use either with a high data rate or a low data rate to each of the SICs. The TCON provides a serial data stream to a SIC, which either uses all of the received data, if it requires high rate data, or relays a portion, e.g., half, of the data to another SIC, which then does not require a separate direct connection to the TCON.
摘要翻译： 用于将数据从定时控制器（TCON）发送到显示器中的多个源驱动器集成电路（SIC）的系统。 该系统适用于每个SIC具有高数据速率或低数据速率。 TCON向SIC提供串行数据流，如果它需要高速率数据，或者将一部分数据例如一半的数据中继到另一个SIC，该SIC将使用所有接收到的数据，然后不需要单独的 直接连接到TCON。
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10.发明申请BODY-BIASED SLICER DESIGN FOR PREDICTIVE DECISION FEEDBACK EQUALIZERS 有权BODY-BIASED SLICER设计用于预测决策反馈均衡器公开(公告)号：US20150116299A1
公开(公告)日：2015-04-30
申请号：US14340463
申请日：2014-07-24
发明人： Mohammad Hekmat , Amir Amirkhany
CPC分类号： H04L25/03057 , G09G5/006 , G09G2310/0297 , G09G2330/021 , H03M1/002 , H03M1/70 , H04L25/03146 , H04L25/03878
摘要： A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.
摘要翻译： 使用一个或多个场效应晶体管（FET）的体偏置来提供预测抽头的偏移的预测判决反馈均衡器。 在一个实施例中，预测判决反馈均衡器的预测抽头包括由差分放大器配置中的两个FET组成的差分放大器，并且控制一个或两个FET的体偏置以在差分放大器中提供偏移。 在一个实施例中，驱动DAC电阻器的电流DAC用于提供体偏置电压，并且包括形成最大可能DAC输出电压的复制电路的反馈电路用于控制电流DAC的电流源的偏置 。
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