A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined for each integrated circuit being tested, corresponding to the read of a high polarization capacitance data state. A number of FRAM cells in the integrated circuit are programmed to that data state, and then read at an elevated temperature, with the number of failing cells compared against a pass/fail threshold to determine whether the integrated circuit is vulnerable to long-term data retention failure.