公开(公告)号：US20150357050A1

公开(公告)日：2015-12-10

申请号：US14519894

申请日：2014-10-21

Applicant: Texas Instruments Incorporated

Inventor： Richard Bailey ,  John A. Rodriguez

IPC: G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50016 ,  G11C11/225

Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined for each integrated circuit being tested, corresponding to the read of a high polarization capacitance data state. A number of FRAM cells in the integrated circuit are programmed to that data state, and then read at an elevated temperature, with the number of failing cells compared against a pass/fail threshold to determine whether the integrated circuit is vulnerable to long-term data retention failure.

Abstract translation: 包括铁电随机存取存储器（FRAM）阵列的集成电路的数据保持可靠性屏幕。 对于正在测试的每个集成电路，对应于高偏振电容数据状态的读取，确定参考电压电平。 集成电路中的多个FRAM单元被编程为该数据状态，然后在升高的温度读取，故障单元的数量与通过/失败阈值进行比较，以确定集成电路是否易受长期数据的影响 保留失败。

公开(公告)号：US09607717B2

公开(公告)日：2017-03-28

申请号：US14519894

申请日：2014-10-21

Applicant: Texas Instruments Incorporated

Inventor： Richard Bailey ,  John A. Rodriguez

IPC: G11C29/50 ,  G11C11/22

CPC classification number: G11C29/50016 ,  G11C11/225

Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined for each integrated circuit being tested, corresponding to the read of a high polarization capacitance data state. A number of FRAM cells in the integrated circuit are programmed to that data state, and then read at an elevated temperature, with the number of failing cells compared against a pass/fail threshold to determine whether the integrated circuit is vulnerable to long-term data retention failure.