A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.