Invention Application
US20160077905A1 Low Power Debug Architecture For System-On-Chips (SoCs) And Systems
有权
用于片上系统(SoC)和系统的低功耗调试架构
- Patent Title: Low Power Debug Architecture For System-On-Chips (SoCs) And Systems
- Patent Title (中): 用于片上系统(SoC)和系统的低功耗调试架构
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Application No.: US14484427Application Date: 2014-09-12
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Publication No.: US20160077905A1Publication Date: 2016-03-17
- Inventor: Sankaran Menon , Babu Trp , Rolf Kuehnis
- Applicant: INTEL CORPORATION
- Main IPC: G06F11/07
- IPC: G06F11/07

Abstract:
In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.
Public/Granted literature
- US09753836B2 Low power debug architecture for system-on-chips (SoCs) and systems Public/Granted day:2017-09-05
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