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公开(公告)号：US10733077B2
公开(公告)日：2020-08-04
申请号：US15856427
申请日：2017-12-28
Applicant: INTEL CORPORATION
Inventor： Sankaran Menon , Krishna Kumar Ganesan , Rolf Kuehnis , Eija Maarit Hillevi Manninen
Abstract: Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.
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公开(公告)号：US09372768B2
公开(公告)日：2016-06-21
申请号：US14141099
申请日：2013-12-26
Applicant: Intel Corporation
Inventor： Jeremy Conner , Sabar Souag , Karunakara Kotary , Victor Ruybalid , Noel Eck , Ramana Rachakonda , Sankaran Menon , Lance Hacking
CPC classification number: G06F11/2268 , G06F11/26 , G06F11/3024 , G06F11/3082 , G06F11/3086 , G06F11/3476 , G06F11/3656 , G06F2201/835 , G06F2201/865
Abstract: Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents.
Abstract translation: 这里描述了调试计算系统的技术。 这些技术可以包括在计算系统中的代理处生成调试数据。 这些技术可以包括将调试数据记录在存储元件处，其中存储元件设置在代理可访问的电路互连的非核心部分中。
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公开(公告)号：US20240385946A1
公开(公告)日：2024-11-21
申请号：US18197255
申请日：2023-05-15
Applicant: Intel Corporation
Inventor： Rakesh Kandula , Rolf Kuehnis , Sankaran Menon
IPC: G06F11/36
Abstract: An example of an apparatus may include circuitry to monitor one or more sensors, determine a debug condition based on the monitored one or more sensors, and provide an indication of the debug condition. In some examples, the apparatus includes further circuitry to adjust a debug operation based at least in part on the provided indication of the debug condition. Other examples are disclosed and claimed.
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公开(公告)号：US20230195416A1
公开(公告)日：2023-06-22
申请号：US17559851
申请日：2021-12-22
Applicant: Intel Corporation
Inventor： Sankaran Menon , Martin Langhammer , Mustansir Fanaswalla , Kuldeep Simha
IPC: G06F7/505 , G06F7/523 , G06F7/501 , H03K19/17736
CPC classification number: G06F7/5057 , G06F7/523 , G06F7/501 , H03K19/17744
Abstract: An integrated circuit is provided that includes via-configured structured logic circuitry and an embedded arithmetic block that interfaces with the via-configured structured logic circuitry to perform an arithmetic function. The embedded arithmetic block includes at least one monolithic arithmetic circuit that can perform the arithmetic function more efficiently or taking up less die space than a comparable circuit formed from the via-configured structured logic circuitry.
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5.发明申请公开(公告)号：US20160077905A1
公开(公告)日：2016-03-17
申请号：US14484427
申请日：2014-09-12
Applicant: INTEL CORPORATION
Inventor： Sankaran Menon , Babu Trp , Rolf Kuehnis
IPC: G06F11/07
CPC classification number: G06F11/3648
Abstract: In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，用于处理器/片上系统（SoC）等的调试架构包括用于接收一个或多个功能调试信号的中央调试单元，所述中央调试单元还被配置为从至少一个固件源接收调试信息 ，至少一个软件源和至少一个硬件源，并输出压缩调试信息; 系统跟踪模块，用于接收压缩的调试信息并对压缩的调试信息进行时间戳; 并行跟踪接口，用于接收时间戳的压缩调试信息，并且并行化时间戳的压缩调试信息; 以及输出单元，用于在多个输出路径之一上输出并行化的时间戳压缩调试信息。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US20240103079A1
公开(公告)日：2024-03-28
申请号：US17954434
申请日：2022-09-28
Applicant: Intel Corporation
Inventor： Rakesh Kandula , Sankaran Menon , Rolf Kuehnis
IPC: G01R31/3185
CPC classification number: G01R31/318544
Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. A device may include computing circuitry and host connectivity registers. Host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. The data contained in host connectivity registers should be always maintained while the computing system is operational. Scan test circuitry may be implemented, providing the ability to test the device while the system is operational. Preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers. By using scan-sealing methods and/or preserving the data in host connectivity registers during in-operation testing, performance and user experience are not degraded.
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公开(公告)号：US20230408581A1
公开(公告)日：2023-12-21
申请号：US17841391
申请日：2022-06-15
Applicant: Intel Corporation
Inventor： Rakesh Kandula , Sankaran Menon , Seng Choon Thor , Shivaprashant Bulusu , Eswar Vadlamani , Ramakrishnan Venkatasubramanian
IPC: G01R31/3185
CPC classification number: G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318572
Abstract: Techniques for interface conversion and unicast for test content, firmware, and software delivery are described. An example apparatus comprises a scan test interface coupled to multiple circuits blocks to perform a scan test for the multiple circuit blocks, and circuitry coupled to input/output (IO) signals of the scan test interface to provide content for the multiple circuit blocks and to deliver a replicated content to multiple endpoints of the multiple circuit blocks (e.g., unicast technology). In another example, the circuitry is coupled to the IO signals of the scan test interface and a system/communication interface to decode packets received at the IO signals and convert the decoded packets to provide content through the system/communication interface for the multiple circuit blocks. Other examples are described and claimed.
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公开(公告)号：US20190042391A1
公开(公告)日：2019-02-07
申请号：US15856427
申请日：2017-12-28
Applicant: INTEL CORPORATION
Inventor： Sankaran Menon , Krishna Kumar Ganesan , Rolf Kuehnis , Eija Maarit Hillevi Manninen
CPC classification number: G06F11/364 , G06F11/302 , G06F11/3428 , G06F11/3452 , G06F11/3466 , G06F11/3636 , G06F2201/865
Abstract: Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.
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公开(公告)号：US09753836B2
公开(公告)日：2017-09-05
申请号：US14484427
申请日：2014-09-12
Applicant: Intel Corporation
Inventor： Sankaran Menon , Babu Trp , Rolf Kuehnis
CPC classification number: G06F11/3648
Abstract: In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.
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公开(公告)号：US11933843B2
公开(公告)日：2024-03-19
申请号：US17377264
申请日：2021-07-15
Applicant: Intel Corporation
Inventor： Keith A. Jones , Wai Mun Ng , Thomas A. Lyda , Subinlal Pk , Sankaran Menon , Vui Yong Liew , Kristan K. Wiseley
IPC: G01R31/317 , G01R31/3183 , G01R31/3185
CPC classification number: G01R31/31721 , G01R31/31705 , G01R31/318314 , G01R31/318533
Abstract: An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.
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